Automatic Tuning of Time Constants in Single Bit Continuous-time Delta-sigma Modulators. - Saurabh Saxena; Prabu Sankar; Shanthi Pavan (ISCAS, 2009)

Rapid-Thermal Annealing of Amorphous Silicon on Oxide Semiconductors. - Saurabh Saxena; Jin Jang (IEICE Trans. Electron., 2010)

A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. - Samira Zali Asl; Saurabh Saxena; Pavan Kumar Hanumolu; Kartikeya Mayaram; Terri S. Fiez (CICC, 2011)

A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW. - Ramin Zanbaghi; Saurabh Saxena; Gabor C. Temes; Terri S. Fiez (CICC, 2011)

A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. - Samira Zali Asl; Saurabh Saxena; Pavan Kumar Hanumolu; Kartikeya Mayaram; Terri S. Fiez (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power. - Ramin Zanbaghi; Saurabh Saxena; Gabor C. Temes; Terri S. Fiez (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter. - Saurabh Saxena; Romesh Kumar Nandwana; Pavan Kumar Hanumolu (CICC, 2013)

15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. - Ahmed Elkholy; Amr Elshazly; Saurabh Saxena; Guanghua Shu; Pavan Kumar Hanumolu (ISSCC, 2014)

8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Tejasvi Anand; Amr Elshazly; Pavan Kumar Hanumolu (ISSCC, 2014)

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. - Romesh Kumar Nandwana; Tejasvi Anand; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Ahmed Elkholy; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (VLSIC, 2014)

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (VLSIC, 2014)

A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis. - Saurabh Saxena; Romesh Kumar Nandwana; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. - Guanghua Shu; Saurabh Saxena; Woo-Seok Choi; Mrunmay Talegaonkar; Rajesh Inti; Amr Elshazly; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. - Ahmed Elkholy; Saurabh Saxena; Romesh Kumar Nandwana; Amr Elshazly; Pavan Kumar Hanumolu (CICC, 2015)

3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. - Tejasvi Anand; Mrunmay Talegaonkar; Ahmed Elkholy; Saurabh Saxena; Amr Elshazly; Pavan Kumar Hanumolu (ISSCC, 2015)

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. - Saurabh Saxena; Guanghua Shu; Romesh Kumar Nandwana; Mrunmay Talegaonkar; Ahmed Elkholy; Tejasvi Anand; Seong Joong Kim; Woo-Seok Choi; Pavan Kumar Hanumolu (VLSIC, 2015)

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. - Tejasvi Anand; Mrunmay Talegaonkar; Ahmed Elkholy; Saurabh Saxena; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. - Romesh Kumar Nandwana; Tejasvi Anand; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Ahmed Elkholy; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

Architectural & circuit level techniques to improve energy efficiency of high speed serial links - Saurabh Saxena (2015)

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Romesh Kumar Nandwana; Ahmed Elkholy; Da Wei; Timir Nandi; Pavan Kumar Hanumolu (ISSCC, 2016)

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. - Ahmed Elkholy; Saurabh Saxena; Romesh Kumar Nandwana; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2016)

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2016)

Large-Scale Evolution of Image Classifiers. - Esteban Real; Sherry Moore; Andrew Selle; Saurabh Saxena; Yutaka I. Leon-Suematsu; Jie Tan 001; Quoc V. Le; Alexey Kurakin (ICML, 2017)

29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. - Romesh Kumar Nandwana; Saurabh Saxena; Ahmed Elkholy; Mrunmay Talegaonkar; Junheng Zhu; Woo-Seok Choi; Ahmed Elmallah; Pavan Kumar Hanumolu (ISSCC, 2017)

Large-Scale Evolution of Image Classifiers. - Esteban Real; Sherry Moore; Andrew Selle; Saurabh Saxena; Yutaka I. Leon-Suematsu; Quoc V. Le; Alex Kurakin (CoRR, 2017)

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. - Saurabh Saxena; Guanghua Shu; Romesh Kumar Nandwana; Mrunmay Talegaonkar; Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2017)

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2017)

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. - Romesh Kumar Nandwana; Saurabh Saxena; Amr Elshazly; Kartikeya Mayaram; Pavan Kumar Hanumolu (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Anomaly Detection During Lithium-ion Battery Qualification Testing. - Saurabh Saxena; Myeongsu Kang; Yinjiao Xing; Michael G. Pecht (ICPHM, 2018)

Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier. - Qadeer A. Khan; Saurabh Saxena; Abirmoya Santra (ISCAS, 2018)

Exploding E-Cigarettes: A Battery Safety Issue. - Saurabh Saxena; Lingxi Kong; Michael G. Pecht (IEEE Access, 2018)

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers. - Ahmed Elkholy; Saurabh Saxena; Guanghua Shu; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2018)

Quantifying the Impact of Prognostic Distance on Average Cost per Cycle. - Saikath Bhattacharya; Lance Fiondella; Saurabh Saxena; Michael G. Pecht (ICPHM, 2019)

The Explosive Nature of Tab Burrs in Li-Ion Batteries. - Xingyan Yao; Saurabh Saxena; Lei Su 002; Michael G. Pecht (IEEE Access, 2019)

Non-Autoregressive Machine Translation with Latent Alignments. - Chitwan Saharia; William Chan; Saurabh Saxena; Mohammad Norouzi 002 (EMNLP (1), 2020)

A 2.5-5GHz Injection-Locked Clock Multiplier with Embedded Phase Interpolator in 65nm CMOS. - R. Gautam; Jaya Deepthi Bandarupalli; Saurabh Saxena (ISCAS, 2020)

Analysis of Specified Capacity in Power Banks. - Weiping Diao; Saurabh Saxena; Michael G. Pecht (IEEE Access, 2020)

An Energy-Efficient 3Gb/s PAM4 Full-Duplex Transmitter With 2-Tap Feed Forward Equalizer. - Shraman Mukherjee; Ashish Das; Sumantra Seth; Saurabh Saxena (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Machine Learning Degradation Model for Electrochemical Capacitors Operated at High Temperature. - Darius Roman; Saurabh Saxena; Jens Bruns; Valentin Robu; Michael G. Pecht; David Flynn (IEEE Access, 2021)

Machine learning pipeline for battery state-of-health estimation. - Darius Roman; Saurabh Saxena; Valentin Robu; Michael G. Pecht; David Flynn (Nat. Mach. Intell., 2021)

Pix2seq: A Language Modeling Framework for Object Detection. - Ting Chen 007; Saurabh Saxena; Lala Li; David J. Fleet; Geoffrey E. Hinton (ICLR, 2022)

A Class-C Injection-Locked Tripler with 48 dB Sub-Harmonic Suppression and 15 fs Additive RMS Jitter in 0.13μm BiCMOS Process. - Sonam Sadhukhan; Pranav Kumar; Arpan Thakkar; Apoorva Bhatia; Saurabh Saxena (ISCAS, 2022)

A Unified Sequence Interface for Vision Tasks. - Ting Chen 007; Saurabh Saxena; Lala Li; Tsung-Yi Lin; David J. Fleet; Geoffrey E. Hinton (NeurIPS, 2022)

Photorealistic Text-to-Image Diffusion Models with Deep Language Understanding. - Chitwan Saharia; William Chan; Saurabh Saxena; Lala Li; Jay Whang; Emily L. Denton; Seyed Kamyar Seyed Ghasemipour; Raphael Gontijo Lopes; Burcu Karagol Ayan; Tim Salimans; Jonathan Ho; David J. Fleet; et al. (NeurIPS, 2022)

A 5-Gb/s PAM4 Voltage Mode Transmitter with Current Mode Continuous Time Linear Equalizer. - Shraman Mukherjee; Sumantra Seth; Saurabh Saxena (VLSID, 2022)

Photorealistic Text-to-Image Diffusion Models with Deep Language Understanding. - Chitwan Saharia; William Chan; Saurabh Saxena; Lala Li; Jay Whang; Emily Denton; Seyed Kamyar Seyed Ghasemipour; Burcu Karagol Ayan; S. Sara Mahdavi; Raphael Gontijo Lopes; Tim Salimans; Jonathan Ho; et al. (CoRR, 2022)

A Surface Energy Balance Model for Predicting Temperature Evolution of Random-Shaped Smoldering Objects in Open Environments. - Saurabh Saxena; Neda Yaghoobian (CoRR, 2022)

A 1.12-1.91 mW/GHz 2.46-4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS. - R. Gautam; Saurabh Saxena (IEEE J. Solid State Circuits, 2022)

A 2.5-5.0-GHz Clock Multiplier With 3.2-4.5-mUIrms Jitter and 0.98-1.06 mW/GHz in 65-nm CMOS. - Jaya Deepthi Bandarupalli; Saurabh Saxena (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.49-9.8 Gb/s 0.1-1V Output Swing Transmitter with 38.4MHz Reference and <30 ns Turn-On Time. - Jaya Deepthi Bandarupalli; Saurabh Saxena (ESSCIRC, 2023)

A Generalist Framework for Panoptic Segmentation of Images and Videos. - Ting Chen 007; Lala Li; Saurabh Saxena; Geoffrey E. Hinton; David J. Fleet (ICCV, 2023)

The Surprising Effectiveness of Diffusion Models for Optical Flow and Monocular Depth Estimation. - Saurabh Saxena; Charles Herrmann; Junhwa Hur; Abhishek Kar; Mohammad Norouzi 002; Deqing Sun; David J. Fleet (NeurIPS, 2023)

A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications. - Snigdha Jakkoju; Deepthi J. Bandarupalli; Anil Srikanth; Saji Thomas; Saurabh Saxena (VLSID, 2023)

A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS. - Shivam Nigam; Mukund Murali; Hari Shanker Gupta; Saurabh Saxena (VLSID, 2023)

Monocular Depth Estimation using Diffusion Models. - Saurabh Saxena; Abhishek Kar; Mohammad Norouzi 002; David J. Fleet (CoRR, 2023)

Zero-Shot Metric Depth with a Field-of-View Conditioned Diffusion Model. - Saurabh Saxena; Junhwa Hur; Charles Herrmann; Deqing Sun; David J. Fleet (CoRR, 2023)

NeRFiller: Completing Scenes via Generative 3D Inpainting. - Ethan Weber; Aleksander Holynski; Varun Jampani; Saurabh Saxena; Noah Snavely; Abhishek Kar; Angjoo Kanazawa (CVPR, 2024)

RoMo: Robust Motion Segmentation Improves Structure from Motion. - Lily Goli; Sara Sabour; Mark J. Matthews; Marcus A. Brubaker; Dmitry Lagun; Alec Jacobson; David J. Fleet; Saurabh Saxena; Andrea Tagliasacchi (CoRR, 2024)

Optimizing Bug Resolution: A Data-Driven Developer Recommendation System. - Saurabh Saxena; Chetna Gupta (Int. J. Perform. Eng., 2024)

A 5.4-7.4 GHz Ultra-Low Jitter Injection-Locked Frequency Tripler With 3rd Harmonic Current Boosting Input Buffer. - Sonam Sadhukhan; Arpan Thakkar; Pranav Kumar; Saurabh Saxena (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

High-Resolution Frame Interpolation with Patch-based Cascaded Diffusion. - Junhwa Hur; Charles Herrmann; Saurabh Saxena; Janne Kontkanen; Wei-Sheng Lai; Yichang Shih; Michael Rubinstein; David J. Fleet; Deqing Sun (AAAI, 2025)

Controlling Space and Time with Diffusion Models. - Daniel Watson; Saurabh Saxena; Lala Li; Andrea Tagliasacchi; David J. Fleet (ICLR, 2025)