Analysis of Programs with Exception-Handling Constructs. - Saurabh Sinha 001; Mary Jean Harrold (ICSM, 1998)

Computation of Interprocedural Control Dependence. - Mary Jean Harrold; Gregg Rothermel; Saurabh Sinha 001 (ISSTA, 1998)

System-Dependence-Graph-Based Slicing of Programs with Arbitrary Interprocedural Control Flow. - Saurabh Sinha 001; Mary Jean Harrold; Gregg Rothermel (ICSE, 1999)

Criteria for Testing Exception-Handling Constructs in Java Programs. - Saurabh Sinha 001; Mary Jean Harrold (ICSM, 1999)

Analysis and Testing of Programs with Exception Handling Constructs. - Saurabh Sinha 001; Mary Jean Harrold (IEEE Trans. Software Eng., 2000)

Interprocedural control dependence. - Saurabh Sinha 001; Mary Jean Harrold; Gregg Rothermel (ACM Trans. Softw. Eng. Methodol., 2001)

Subsumption of program entities for efficient coverage and monitoring. - Raúl A. Santelices; Saurabh Sinha 001; Mary Jean Harrold (SOQUA, 2006)

Compact modeling of carbon nanotube transistor for early stage process-design exploration. - Asha Balijepalli; Saurabh Sinha 001; Yu Cao 001 (ISLPED, 2007)

A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. - Saurabh Sinha 001; Asha Balijepalli; Yu Cao 001 (ISQED, 2008)

Enabling resonant clock distribution with scaled on-chip magnetic inductors. - Saurabh Sinha 001; Wei Xu; Jyothi Bhaskarr Velamala; Tawab Dastagir; Bertan Bakkaloglu; Hongbin Yu; Yu Cao 001 (ICCD, 2009)

Accurate Interprocedural Null-Dereference Analysis for Java. - Mangala Gowri Nanda; Saurabh Sinha 001 (ICSE, 2009)

Efficient Testing of Service-Oriented Applications Using Semantic Service Stubs. - Senthil Mani; Vibha Singhal Sinha; Saurabh Sinha 001; Pankaj Dhoolia; Debdoot Mukherjee; Soham Chakraborty 001 (ICWS, 2009)

Fault localization and repair for Java runtime exceptions. - Saurabh Sinha 001; Hina Shah; Carsten Görg; Shujuan Jiang; Mijung Kim; Mary Jean Harrold (ISSTA, 2009)

Demystifying model transformations: an approach based on automated rule inference. - Mangala Gowri Nanda; Senthil Mani; Vibha Singhal Sinha; Saurabh Sinha 001 (OOPSLA, 2009)

The Predictive Technology Model in the Late Silicon Era and Beyond. - Yu Cao 001; Asha Balijepalli; Saurabh Sinha 001; Chi-Chao Wang; Wenping Wang 004; Wei Zhao (Found. Trends Electron. Des. Autom., 2009)

From Informal Process Diagrams to Formal Process Models. - Debdoot Mukherjee; Pankaj Dhoolia; Saurabh Sinha 001; Aubrey J. Rembert; Mangala Gowri Nanda (BPM, 2010)

Debugging Model-Transformation Failures Using Dynamic Tainting. - Pankaj Dhoolia; Senthil Mani; Vibha Singhal Sinha; Saurabh Sinha 001 (ECOOP, 2010)

Making defect-finding tools work for you. - Mangala Gowri Nanda; Monika Gupta 002; Saurabh Sinha 001; Satish Chandra 001; David Schmidt; Pradeep Balachandran (ICSE (2), 2010)

Automated Bug Neighborhood Analysis for Identifying Incomplete Bug Fixes. - Mijung Kim; Saurabh Sinha 001; Carsten Görg; Hina Shah; Mary Jean Harrold; Mangala Gowri Nanda (ICST, 2010)

BUGINNINGS: identifying the origins of a bug. - Vibha Singhal Sinha; Saurabh Sinha 001; Swathi Rao (ISEC, 2010)

Workload-aware neuromorphic design of low-power supply voltage controller. - Saurabh Sinha 001; Jounghyuk Suh; Bertan Bakkaloglu; Yu Cao 001 (ISLPED, 2010)

Automated support for repairing input-model faults. - Senthil Mani; Vibha Singhal Sinha; Pankaj Dhoolia; Saurabh Sinha 001 (ASE, 2010)

A workload-aware neuromorphic controller for dynamic power and thermal management. - Saurabh Sinha 001; Jounghyuk Suh; Bertan Bakkaloglu; Yu Cao 001 (AHS, 2011)

Serving Information Needs in Business Process Consulting. - Monika Gupta 002; Debdoot Mukherjee; Senthil Mani; Vibha Singhal Sinha; Saurabh Sinha 001 (BPM, 2011)

Outsourced, Offshored Software-Testing Practice: Vendor-Side Experiences. - Hina Shah; Saurabh Sinha 001; Mary Jean Harrold (ICGSE, 2011)

Entering the circle of trust: developer initiation as committers in open-source projects. - Vibha Singhal Sinha; Senthil Mani; Saurabh Sinha 001 (MSR, 2011)

Workload-Aware Neuromorphic Design of the Power Controller. - Saurabh Sinha 001; Jounghyuk Suh; Bertan Bakkaloglu; Yu Cao 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Exploring sub-20nm FinFET design with predictive technology models. - Saurabh Sinha 001; Greg Yeric; Vikas Chandra; Brian Cline; Yu Cao 001 (DAC, 2012)

Automating test automation. - Suresh Thummalapenta; Saurabh Sinha 001; Nimit Singhania; Satish Chandra 001 (ICSE, 2012)

Design benchmarking to 7nm with FinFET predictive technology models. - Saurabh Sinha 001; Brian Cline; Greg Yeric; Vikas Chandra; Yu Cao 001 (ISLPED, 2012)

Efficiently scripting change-resilient tests. - Suresh Thummalapenta; Nimit Singhania; Pranavadatta Devaki; Saurabh Sinha 001; Satish Chandra 001; Achin K. Das; Srinivas Mangipudi (SIGSOFT FSE, 2012)

The past present and future of design-technology co-optimization. - Greg Yeric; Brian Cline; Saurabh Sinha 001; David Pietromonaco; Vikas Chandra; Rob Aitken (CICC, 2013)

Efficient and change-resilient test automation: an industrial case study. - Suresh Thummalapenta; Pranavadatta Devaki; Saurabh Sinha 001; Satish Chandra 001; Sivagami Gnanasundaram; Deepa D. Nagaraj; Sampathkumar Sathishkumar (ICSE, 2013)

Guided test generation for web applications. - Suresh Thummalapenta; K. Vasanta Lakshmi; Saurabh Sinha 001; Nishant Sinha 001; Satish Chandra 001 (ICSE, 2013)

Software services: a research roadmap. - Satish Chandra 001; Vibha Singhal Sinha; Saurabh Sinha 001; Krishna Ratakonda (FOSE, 2014)

Operational abstractions of model transforms. - Vibha Singhal Sinha; Pankaj Dhoolia; Senthil Mani; Saurabh Sinha 001 (ISEC, 2014)

Physical design and FinFETs. - Robert C. Aitken; Greg Yeric; Brian Cline; Saurabh Sinha 001; Lucian Shifren; Imran Iqbal; Vikas Chandra (ISPD, 2014)

Robust test automation using contextual clues. - Rahulkrishna Yandrapally; Suresh Thummalapenta; Saurabh Sinha 001; Satish Chandra 001 (ISSTA, 2014)

Global software testing under deadline pressure: Vendor-side experiences. - Hina Shah; Mary Jean Harrold; Saurabh Sinha 001 (Inf. Softw. Technol., 2014)

Automated Modularization of GUI Test Cases. - Rahulkrishna Yandrapally; Giriprasad Sridhara; Saurabh Sinha 001 (ICSE (1), 2015)

Test Generation from Business Rules. - Simon Holm Jensen; Suresh Thummalapenta; Saurabh Sinha 001; Satish Chandra 001 (ICST, 2015)

Power benefit study of monolithic 3D IC at the 7nm technology node. - Kyungwook Chang; Kartik Acharya; Saurabh Sinha 001; Brian Cline; Greg Yeric; Sung Kyu Lim (ISLPED, 2015)

Circuit design perspectives for Ge FinFET at 10nm and beyond. - Saurabh Sinha 001; Lucian Shifren; Vikas Chandra; Brian Cline; Greg Yeric; Robert C. Aitken; Bingjie Cheng; Andrew R. Brown; Craig Riddet; C. Alexandar; Campbell Millar; Asen Asenov (ISQED, 2015)

Match-making for monolithic 3D IC: finding the right technology node. - Kyungwook Chang; Saurabh Sinha 001; Brian Cline; Greg Yeric; Sung Kyu Lim (DAC, 2016)

Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability. - Nathaniel Ross Pinckney; Lucian Shifren; Brian Cline; Saurabh Sinha 001; Supreet Jeloka; Ronald G. Dreslinski; Trevor N. Mudge; Dennis Sylvester; David T. Blaauw (DAC, 2016)

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. - Kyungwook Chang; Saurabh Sinha 001; Brian Cline; Raney Southerland; Michael Doherty; Greg Yeric; Sung Kyu Lim (ICCAD, 2016)

Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. - Kwang Min Kim; Saurabh Sinha 001; Brian Cline; Greg Yeric; Sung Kyu Lim (ISLPED, 2016)

Monolithic 3D IC design: Power, performance, and area impact at 7nm. - Kartik Acharya; Kyungwook Chang; Bon Woong Ku; Shreepad Panth; Saurabh Sinha 001; Brian Cline; Greg Yeric; Sung Kyu Lim (ISQED, 2016)

Lessons from the tech transfer trenches. - Satish Chandra 001; Suresh Thummalapenta; Saurabh Sinha 001 (Commun. ACM, 2016)

Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. - Robert C. Aitken; Vikas Chandra; Brian Cline; Shidhartha Das; David Pietromonaco; Lucian Shifren; Saurabh Sinha 001; Greg Yeric (IET Comput. Digit. Tech., 2016)

ASAP7: A 7-nm finFET predictive process design kit. - Lawrence T. Clark; Vinay Vashishtha; Lucian Shifren; Aditya Gujja; Saurabh Sinha 001; Brian Cline; Chandarasekaran Ramamurthy; Greg Yeric (Microelectron. J., 2016)

Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper). - Kyungwook Chang; Bon Woong Ku; Saurabh Sinha 001; Sung Kyu Lim (ICCAD, 2017)

Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). - Xiaoqing Xu; Nishi Shah; Andrew Evans; Saurabh Sinha 001; Brian Cline; Greg Yeric (ICCAD, 2017)

Frequency and time domain analysis of power delivery network for monolithic 3D ICs. - Kyungwook Chang; Shidhartha Das; Saurabh Sinha 001; Brian Cline; Greg Yeric; Sung Kyu Lim (ISLPED, 2017)

Impact of FinFET on Near-Threshold Voltage Scalability. - Nathaniel Ross Pinckney; Supreet Jeloka; Ronald G. Dreslinski; Trevor N. Mudge; Dennis Sylvester; David T. Blaauw; Lucian Shifren; Brian Cline; Saurabh Sinha 001 (IEEE Des. Test, 2017)

Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. - Kyungwook Chang; Kartik Acharya; Saurabh Sinha 001; Brian Cline; Greg Yeric; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. - Divya Prasad; Saurabh Sinha 001; Brian Cline; Steve Moore; Azad Naeemi (DAC, 2018)

Standard Cell Library Design and Optimization Methodology for ASAP7 PDK. - Xiaoqing Xu; Nishi Shah; Andrew Evans; Saurabh Sinha 001; Brian Cline; Greg Yeric (CoRR, 2018)

Enhanced 3D Implementation of an Arm® Cortex®-A Microprocessor. - Xiaoqing Xu; Mudit Bhargava; Steve Moore; Saurabh Sinha 001; Brian Cline (ISLPED, 2019)

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. - Kyungwook Chang; Shidhartha Das; Saurabh Sinha 001; Brian Cline; Greg Yeric; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs. - Lingjun Zhu; Kyungwook Chang; Dusan Petranovic; Saurabh Sinha 001; Yun Seop Yu; Sung Kyu Lim (ISPD, 2020)

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. - Saurabh Sinha 001; Xiaoqing Xu; Mudit Bhargava; Shidhartha Das; Brian Cline; Greg Yeric (CoRR, 2020)

Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology. - Rahul Mathur; Chien-Ju Chao; Rossana Liu; Nikhil Tadepalli; Pranavi Chandupatla; Shawn Hung; Xiaoqing Xu; Saurabh Sinha 001; Jaydeep Kulkarni (CoRR, 2020)

3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. - Rahul Mathur; Mudit Bhargava; Heath Perry; Alberto Cestero; Frank Frederick; Shawn Hung; Chien-Ju Chao; Daniel Smith; Daniel Fisher; Norman Robson; Xiaoqing Xu; Pranavi Chandupatla; et al. (CICC, 2021)

Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. - Chi-Shuen Lee; Brian Cline; Saurabh Sinha 001; Greg Yeric; H.-S. Philip Wong (CoRR, 2021)

High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors. - Lingjun Zhu; Lennart Bamberg; Sai Surya Kiran Pentapati; Kyungwook Chang; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Brian Cline; Saurabh Sinha 001; Xiaoqing Xu; Alberto García-Ortiz; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. - Kyungwook Chang; Saurabh Sinha 001; Brian Cline; Greg Yeric; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)