A sub-2W 10GBase-T analog front-end in 40nm CMOS process. - Tarun Gupta; Frank Yang; Dong Wang; Ali Tabatabaei; Ramesh Singh; Hesam Amir Aslanzadeh; Alireza Khalili; Saurabh Vats; Susan Arno; Sean Campeau (ISSCC, 2012)

Selection of optimal electronic toll collection system for India: A subjective-fuzzy decision making approach. - Saurabh Vats; Gaurav Vats; Rahul Vaish; Varun Kumar (Appl. Soft Comput., 2014)

Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver. - Shankarram Athreya; Hiva Hedayati; Shayan Kazemkhani; Yanfei Chen; Saurabh Vats; Michael D. Scott 002; Bart Zeydel; Peter Keller; Jian Wang; Bhaskarareddy Avula; Boris Murmann; Echere Iroaga (ESSCIRC, 2018)

Beyond the Beachfront: Integration of Silicon Photonic I/Os under a High-Power ASIC. - Subal Sahni; Abhijit Abhyankar; Ankur Aggarwal; Nikos Bamiedakis; Zoltan Bekker; Mohamed Benromdhane; Nadav Bergstein; Ties Bos; Christopher Davies; Andrew Gimlett; Xiaoping Han; Kelin Lee; et al. (OFC, 2024)

Photonic Fabric for Memory and Compute Disaggregation. - Subal Sahni; Ankur Aggarwal; Nadav Bergstein; Trung Diep; Jing Ding; Andrew Gimlett; Ravi Mahatme; Parmanand Mishra; Sujit Ramachandra; Matteo Staffaroni; Angelina Totovic; Saurabh Vats; et al. (OFC, 2025)