Buffer assignment for data driven architectures. - Dhiraj K. Pradhan; Mitrajit Chatterjee; Savita Banerjee (ICCAD, 1993)

Signal Transition Graph Transformations for Initializability. - Savita Banerjee; Rabindra K. Roy; Srimat T. Chakradhar; Dhiraj K. Pradhan (EDAC-ETC-EUROASIC, 1994)

Initialization Isuues in the Synthesis of Asynchronous Circuits. - Savita Banerjee; Rabindra K. Roy; Srimat T. Chakradhar; Dhiraj K. Pradhan (ICCD, 1994)

Synchronous Test Generation Model for Asynchronous Circuits. - Savita Banerjee; Srimat T. Chakradhar; Rabindra K. Roy (VLSI Design, 1996)

Initialization issues in asynchronous circuit synthesis. - Savita Banerjee; Rabindra K. Roy; Srimat T. Chakradhar (J. Electron. Test., 1996)

Synthesis of initializable asynchronous circuits. - Srimat T. Chakradhar; Savita Banerjee; Rabindra K. Roy; Dhiraj K. Pradhan (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Buffer Assignment Algorithms on Data Driven ASICs. - Mitrajit Chatterjee; Savita Banerjee; Dhiraj K. Pradhan (IEEE Trans. Computers, 2000)

Layout-aware Illinois Scan design for high fault coverage coverage. - Savita Banerjee; Jimson Mathew; Dhiraj K. Pradhan; Saraju P. Mohanty (ISQED, 2010)

On the synthesis of attack tolerant cryptographic hardware. - Jimson Mathew; Savita Banerjee; Hafizur Rahaman 001; Dhiraj K. Pradhan; Saraju P. Mohanty; Abusaleh M. Jabir (VLSI-SoC, 2010)