Energy efficient lossless image compression with prediction-based transform. - Savithra Eratne; Sebastian Puthenpurayil; Eugene John (APCCAS, 2008)

Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm. - Pradeep S. Nair; Savithra Eratne; Eugene John (APCCAS, 2008)

Effects of Register File Organization on Leakage Power Consumption. - Pradeep S. Nair; Savithra Eratne; Eugene John (CDES, 2008)

Energy Efficiency of Data Compression with Wavelets. - Savithra Eratne; Sebastian Puthenpurayil; Eugene John (IPCV, 2008)

Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase. - Savithra Eratne; Claudia Romo; Eugene John (CDES, 2010)

Leakage and Access Time Tradeoffs for Cache in High Performance Microprocessors. - Savithra Eratne; Claudia Romo; Eugene John; Byeong Kil Lee (CDES, 2010)

Reducing thermal hotspots in microprocessors with expanded component sizing. - Savithra Eratne; Eugene John; Byeong Kil Lee (MWSCAS, 2012)

Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance. - Pradeep S. Nair; Savithra Eratne; Eugene B. John (J. Low Power Electron., 2012)

A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors. - Savithra Eratne; Pradeep S. Nair; Eugene John (J. Low Power Electron., 2015)