A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. - Savithri Sundareswaran; David T. Blaauw; Abhijit Dharchoudhury (VLSI Design, 1999)

Slope Propagation in Static Timing Analysis. - David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Chanhee Oh; Rajendran Panda (ICCAD, 2000)

An Assertion Based Technique for Transistor Level Dynamic Power Estimation. - Savithri Sundareswaran; R. Venkatesan; S. Bhaskar (VLSI Design, 2000)

On the interaction of power distribution network with substrate. - Rajendran Panda; Savithri Sundareswaran; David T. Blaauw (ISLPED, 2001)

Slope propagation in static timing analysis. - David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Statistical delay computation considering spatial correlations. - Aseem Agarwal; David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Min Zhao 001; Kaushik Gala; Rajendran Panda (ASP-DAC, 2003)

Vectorless Analysis of Supply Noise Induced Delay Variation. - Sanjay Pant; David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Rajendran Panda (ICCAD, 2003)

Impact of Low-Impedance Substrate on Power Supply Integrity. - Rajendran Panda; Savithri Sundareswaran; David T. Blaauw (IEEE Des. Test Comput., 2003)

A stochastic approach To power grid analysis. - Sanjay Pant; David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Rajendran Panda (DAC, 2004)

A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. - Min Zhao 001; Rajendran Panda; Savithri Sundareswaran; Shu Yan; Yuhong Fu (DAC, 2006)

Optimal placement of power-supply pads and pins. - Min Zhao 001; Yuhong Fu; Vladimir Zolotov; Savithri Sundareswaran; Rajendran Panda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. - Min Zhao 001; Rajendran Panda; Ben Reschke; Yuhong Fu; Trudi Mewett; Sri Chandrasekaran; Savithri Sundareswaran; Shu Yan (DAC, 2007)

A novel technique for incremental analysis of on-chip power distribution networks. - Yuhong Fu; Rajendran Panda; Ben Reschke; Savithri Sundareswaran; Min Zhao 001 (ICCAD, 2007)

Small-Delay Defect Detection in the Presence of Process Variations. - Rajeshwary Tayade; Savithri Sundareswaran; Jacob A. Abraham (ISQED, 2007)

Analyzing the risk of timing modeling based on path delay tests. - Pouria Bastani; Benjamin N. Lee; Li-C. Wang; Savithri Sundareswaran; Magdy S. Abadir (ITC, 2007)

Faster statistical cell characterization using adjoint sensitivity analysis. - Ben Gu; Kiran K. Gullapalli; Yun Zhang; Savithri Sundareswaran (CICC, 2008)

Transistor-Specific Delay Modeling for SSTA. - Brian Cline; Kaviraj Chopra; David T. Blaauw; Andres Torres; Savithri Sundareswaran (DATE, 2008)

Characterization of Standard Cells for Intra-Cell Mismatch Variations. - Savithri Sundareswaran; Jacob A. Abraham; Alexandre Ardelea; Rajendran Panda (ISQED, 2008)

A timing methodology considering within-die clock skew variations. - Savithri Sundareswaran; Lucie Nechanicka; Rajendran Panda; Sergey Gavrilov; Roman A. Solovyev; Jacob A. Abraham (SoCC, 2008)

Characterization of sequential cells for constraint sensitivities. - Savithri Sundareswaran; Rajendran Panda; Jacob A. Abraham; Yun Zhang; Amit Mittal (ISQED, 2009)

Total sensitivity based dfm optimization of standard library cells. - Yongchan Ban; Savithri Sundareswaran; David Z. Pan (ISPD, 2010)

A sensitivity-aware methodology to improve cell layouts for DFM guidelines. - Savithri Sundareswaran; Robert L. Maziasz; Vladimir Rozenfeld; Mikhail Sotnikov; Mukhanov Konstantin (ISQED, 2011)

Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating. - Tong Xu 004; Peng Li 001; Savithri Sundareswaran (ACM Trans. Design Autom. Electr. Syst., 2015)

SLECTS: Slew-Driven Clock Tree Synthesis. - Weicheng Liu; Can Sitik; Emre Salman; Baris Taskin; Savithri Sundareswaran; Benjamin Huang (IEEE Trans. Very Large Scale Integr. Syst., 2019)