A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis. - Sayak Ray; Pallab Dasgupta; P. P. Chakrabarti 001 (VLSI Design, 2007)

Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. - Jiang Long; Sayak Ray; Baruch Sterin; Alan Mishchenko; Robert K. Brayton (DIFTS@FMCAD, 2011)

Scalable progress verification in credit-based flow-control systems. - Sayak Ray; Robert K. Brayton (DATE, 2012)

Mapping into LUT structures. - Sayak Ray; Alan Mishchenko; Niklas Eén; Robert K. Brayton; Stephen Jang; Chao Chen (DATE, 2012)

A dynamic assertion-based verification platform for validation of UML designs. - Ansuman Banerjee; Sayak Ray; Pallab Dasgupta; P. P. Chakrabarti 001; S. Ramesh 002; P. Vignesh V. Ganesan (ACM SIGSOFT Softw. Eng. Notes, 2012)

Ranking structure in communication fabrics. - Sayak Ray; Robert K. Brayton (MEMOCODE, 2013)

Scalable Model Checking Beyond Safety - A Communication Fabric Perspective. - Sayak Ray (2013)

ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. - Aadithya V. Karthik; Sayak Ray; Pierluigi Nuzzo; Alan Mishchenko; Robert K. Brayton; Jaijeet Roychowdhury (ASP-DAC, 2014)

NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract). - Aadithya V. Karthik; David Soloveichik; Sayak Ray; Baruch Sterin; Alan Mishchenko; Robert K. Brayton; Jaijeet Roychowdhury (BCB, 2014)

Effective abstraction for response proof of communication fabrics. - Sayak Ray; Sharad Malik (NOCS, 2014)

BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies. - Aadithya V. Karthik; Sayak Ray; Jaijeet Roychowdhury (ASP-DAC, 2015)

Template-based Synthesis of Instruction-Level Abstractions for SoC Verification. - Pramod Subramanyan; Yakir Vizel; Sayak Ray; Sharad Malik (FMCAD, 2015)

Evaluating the security of logic encryption algorithms. - Pramod Subramanyan; Sayak Ray; Sharad Malik (HOST, 2015)

Malware detection using machine learning based analysis of virtual memory access patterns. - Zhixing Xu; Sayak Ray; Pramod Subramanyan; Sharad Malik (DATE, 2017)

Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. - Bo-Yuan Huang 001; Sayak Ray; Aarti Gupta; Jason M. Fung; Sharad Malik (DAC, 2018)

Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs. - Sayak Ray; Nishant Ghosh; Ramya Jayaram Masti; Arun K. Kanuparthi; Jason M. Fung (DAC, 2019)

Verification of Authenticated Firmware Loaders. - Sujit Kumar Muduli; Pramod Subramanyan; Sayak Ray (FMCAD, 2019)

Verification of Authenticated Firmware Load. - Sujit Kumar Muduli; Pramod Subramanyan; Sayak Ray (IACR Cryptol. ePrint Arch., 2019)

Automating hardware security property generation: invited. - Ryan Kastner; Francesco Restuccia 002; Andres Meza 001; Sayak Ray; Jason M. Fung; Cynthia Sturton (DAC, 2022)

Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK. - Anupam Golder; Debayan Das; Santosh Ghosh; Avinash Varna 001; Majid Sabbagh; Sayak Ray; Rana Elnaggar; Joseph Friel; Daniel Dinu; Jason M. Fung (DAC, 2023)

Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL. - Tobias Jauch; Alex Wezel; Mohammad Rahmani Fadiheh; Philipp Schmitz; Sayak Ray; Jason M. Fung; Christopher W. Fletcher; Dominik Stoffel; Wolfgang Kunz (ICCAD, 2023)

An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. - Mohammad Rahmani Fadiheh; Alex Wezel; Johannes Müller 006; Jörg Bormann; Sayak Ray; Jason M. Fung; Subhasish Mitra; Dominik Stoffel; Wolfgang Kunz (IEEE Trans. Computers, 2023)

Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS. - Debayan Das; Majid Sabbagh; Rana Elnaggar; Guang Chen; Sayak Ray; Jason M. Fung (VLSID, 2024)