Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm. - Animesh Gupta; Sayan Kumar; Viveka Konandur Rajanna; Sachin Taneja; Massimo Alioto (VLSI Technology and Circuits, 2023)

A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling. - Sayan Kumar; Patchara Sawakewang; Teerachot Siriburanon; Robert Bogdan Staszewski (VLSI Technology and Circuits, 2024)

Trifilar-Transformer-Coupled Series-Resonance Oscillator with Enhanced Tuning Range. - Sumit Dash; Sayan Kumar; Teerachot Siriburanon; Robert Bogdan Staszewski (ISCAS, 2025)

A 4kb 4T eDRAM with Balanced Retention Time Adjustment. - Sayan Kumar; Dennis Andrade-Miceli; Chawin Khongprasongsiri; Teerachot Siriburanon; Robert Bogdan Staszewski (ISCAS, 2025)

A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations. - Sayan Kumar; Teerachot Siriburanon; Sumit Dash; Patchara Sawakewang; Shuja Andrabi; Jon Strange; Khurram Muhammad; Chih-Ming Hung; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2025)