A Novel Digital Voltage Controller for Single-Phase PFC Rectifiers. - Dawood Shekari Beyragh; Sayed Masoud Sayedi; Hamid Reza Karshenas (CCECE, 2006)

A nonlinearity error calibration technique based on an opamp distortion modeling. - Armin Jalili; Sayed Masoud Sayedi (APCCAS, 2008)

A frequency based digital background calibration technique for pipelined ADCs. - Armin Jalili; Sayed Masoud Sayedi; Rasoul Dehghani; Ebrahim Farshidi (ICECS, 2008)

A 1.2 V current-mode true RMS-DC converter based on the floating gate MOS translinear principle. - Ebrahim Farshidi; Sayed Masoud Sayedi (Microelectron. J., 2008)

An Analog VLSI Architecture for High Speed, Low Power Object Tracking. - Mehdi Habibi; Masoud Sayedi (Int. J. Distributed Sens. Networks, 2009)

Calibration of high-resolution flash ADCS based on histogram test methods. - Armin Jalili; Sayed Masoud Sayedi; J. Jacob Wikner; Kent Palmkvist; Mark Vesterbacka (ICECS, 2010)

Geometric centre tracking of tagged objects using a low power demodulation smart vision sensor. - Mehdi Habibi; Masoud Sayedi (IET Circuits Devices Syst., 2010)

Low-power dual-edge triggered state-retention scan flip-flop. - Hossein Karimiyan; Sayed Masoud Sayedi; Hossein Saidi 001 (IET Comput. Digit. Tech., 2010)

Asynchronous demodulation CMOS sensor for object labeling and its application in robotics. - Mehdi Habibi; Sayed Masoud Sayedi (Ind. Robot, 2010)

Asynchronous demodulation technique for use in vision sensor image classification and segmentation. - Mehdi Habibi; Sayed Masoud Sayedi (Int. J. Circuit Theory Appl., 2011)

A nonlinearity error calibration technique for pipelined ADCs. - Armin Jalili; Sayed Masoud Sayedi; J. Jacob Wikner; Abolghasem Zeidaabadi Nezhad (Integr., 2011)

Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs. - Armin Jalili; Sayed Masoud Sayedi; J. Jacob Wikner (Microelectron. J., 2011)

Design of a neuromorphic edge detector vision chip with color and intensity change disambiguation. - Hesam Ahmadi; Sayed Masoud Sayedi (CCECE, 2012)

Fault coverage improvement and test vector generation for combinational circuits using spectral analysis. - Mehrnaz Ahmady; Sayed Masoud Sayedi (CCECE, 2012)

A low power D3L 16-bit radix- 4 pipelined SRT divider. - Shirin Pourashraf; Sayed Masoud Sayedi (CCECE, 2012)

Implementation of a low power 16-bit radix-4 pipelined SRT divider using a modified Split-Path Data Driven Dynamic Logic (SPD3L) structure. - Shirin Pourashraf; Sayed Masoud Sayedi (Microelectron. J., 2013)

High-speed and pipelined finite field bit-parallel multiplier over GF(2m) for elliptic curve cryptosystems. - Bahram Rashidi; Reza Rezaeian Farashahi; Sayed Masoud Sayedi (ISCISC, 2014)

FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm. - Reza Rezaeian Farashahi; Bahram Rashidi; Sayed Masoud Sayedi (Microelectron. J., 2014)

A face detection method based on kernel probability map. - Mohammad Reza Mahmoodi; Sayed Masoud Sayedi (Comput. Electr. Eng., 2015)

Efficient and Low-complexity Hardware Architecture of Gaussian Normal Basis Multiplication over GF(2m) for Elliptic Curve Cryptosystems. - Bahram Rashidi; Sayed Masoud Sayedi; Reza Rezaeian Farashahi (IACR Cryptol. ePrint Arch., 2015)

Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields. - Bahram Rashidi; Reza Rezaeian Farashahi; Sayed Masoud Sayedi (ISC Int. J. Inf. Secur., 2015)

High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m). - Bahram Rashidi; Sayed Masoud Sayedi; Reza Rezaeian Farashahi (IACR Cryptol. ePrint Arch., 2016)

Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2 m ). - Bahram Rashidi; Sayed Masoud Sayedi; Reza Rezaeian Farashahi (IET Comput. Digit. Tech., 2016)

A low-power wide tuning-range CMOS current-controlled oscillator. - Kourosh Hassanli; Sayed Masoud Sayedi; Rasoul Dehghani; Armin Jalili; J. Jacob Wikner (Integr., 2016)

An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m). - Bahram Rashidi; Sayed Masoud Sayedi; Reza Rezaeian Farashahi (Integr., 2016)

High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems. - Bahram Rashidi; Sayed Masoud Sayedi; Reza Rezaeian Farashahi (Microelectron. J., 2016)

High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves. - Bahram Rashidi; Reza Rezaeian Farashahi; Sayed Masoud Sayedi (IACR Cryptol. ePrint Arch., 2017)

Efficient and low-complexity hardware architecture of Gaussian normal basis multiplication over GF(2 m ) for elliptic curve cryptosystems. - Bahram Rashidi; Sayed Masoud Sayedi; Reza Rezaeian Farashahi (IET Circuits Devices Syst., 2017)

Full-custom hardware implementation of point multiplication on binary Edwards curves for application-specific integrated circuit elliptic curve cryptosystem applications. - Bahram Rashidi; Sayed Masoud Sayedi; Reza Rezaeian Farashahi (IET Circuits Devices Syst., 2017)

High-performance and high-speed implementation of polynomial basis Itoh-Tsujii inversion algorithm over GF(2 m ). - Bahram Rashidi; Reza Rezaeian Farashahi; Sayed Masoud Sayedi (IET Inf. Secur., 2017)

Color-based skin segmentation in videos using a multi-step spatial method. - Mohammad Reza Mahmoodi; Sayed Masoud Sayedi; Fariba Karimi 003 (Multim. Tools Appl., 2017)

SystemC-AMS modeling of photodiode based on PWL technique to be used in energy harvesting CMOS image sensor. - Mohammad Radpour; Sayed Masoud Sayedi (Integr., 2018)

A Low-Complexity Hardware for Deterministic Compressive Sensing Reconstruction. - Mohammad Fardad; Sayed Masoud Sayedi; Ehsan Yazdian (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Hardware Implementation of Iterative Method With Adaptive Thresholding for Random Sampling Recovery of Sparse Signals. - Mohammad Fardad; Sayed Masoud Sayedi; Ehsan Yazdian (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A structured review of sparse fast Fourier transform algorithms. - Elias Rajaby; Sayed Masoud Sayedi (Digit. Signal Process., 2022)

Hardware design and implementation of high-efficiency cube-root of complex numbers. - Elias Rajaby; Sayed Masoud Sayedi; Ehsan Yazdian (Microprocess. Microsystems, 2023)

Spintronic Content Addressable Memory With Integrated Boolean Logic and Arithmetic Functions. - Zahra Mehdizadeh Taheri; Sayed Masoud Sayedi; Mohammad Hossein Moaiyeri (IEEE Access, 2025)