Testing QCA Modular Logic. - Sayeeda Sultana; Shahriar Al-Imam; Katarzyna Radecka (ICECS, 2006)

Design for Testability of QCA Logic Under Stuck-at-value Fault Model. - Sayeeda Sultana; Shahriar Al-Imam; Katarzyna Radecka (J. Multiple Valued Log. Soft Comput., 2008)

Positive Davio-based synthesis algorithm for reversible logic. - Yu Pang; Shaoquan Wang; Zhilong He; Jinzhao Lin; Sayeeda Sultana; Katarzyna Radecka (ICCD, 2011)

A study on relating redundancy removal in classical circuits to reversible mapping. - Sayeeda Sultana; Katarzyna Radecka; Yu Pang (ICCD, 2011)

Reversible implementation of square-root circuit. - Sayeeda Sultana; Katarzyna Radecka (ICECS, 2011)

A novel method of synthesizing reversible logic. - Yu Pang; Jinzhao Lin; Sayeeda Sultana; Katarzyna Radecka (ISCAS, 2011)

Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network. - Sayeeda Sultana; Katarzyna Radecka (ISMVL, 2011)

SAT-based reversible gate/wire replacement fault testing. - Sayeeda Sultana; Atena Roshan Fekr; Katarzyna Radecka (MWSCAS, 2013)

Testing reversible adder/subtractor for missing control points. - Sayeeda Sultana; Katarzyna Radecka (MWSCAS, 2013)