Reducing signal-bias from MAD estimated noise level for DCT speech enhancement. - Md. Kamrul Hasan 001; Sayeef S. Salahuddin; M. Rezwan Khan (Signal Process., 2004)

Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement. - Jing Li 073; Haixin Liu; Sayeef S. Salahuddin; Kaushik Roy 001 (CICC, 2008)

Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. - Jing Li 073; Charles Augustine; Sayeef S. Salahuddin; Kaushik Roy 001 (DAC, 2008)

Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study. - Subho Chatterjee; Sayeef S. Salahuddin; Satish Kumar; Saibal Mukhopadhyay (ISLPED, 2010)

Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes. - Subho Chatterjee; Sayeef S. Salahuddin; Saibal Mukhopadhyay (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective. - Jing Li 073; Patrick Ndai; Ashish Goel; Sayeef S. Salahuddin; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Performance assessment of partially unzipped carbon nanotube field-effect transistors. - Youngki Yoon; Sayeef S. Salahuddin (NANOARCH, 2011)

Electrothermal analysis of spin-transfer-torque random access memory arrays. - Subho Chatterjee; Sayeef S. Salahuddin; Satish Kumar; Saibal Mukhopadhyay (ACM J. Emerg. Technol. Comput. Syst., 2013)

Nonvolatile memory design based on ferroelectric FETs. - Sumitha George; Kaisheng Ma; Ahmedullah Aziz; Xueqing Li 002; Asif Islam Khan; Sayeef S. Salahuddin; Meng-Fan Chang; Suman Datta; John Sampson; Sumeet Kumar Gupta; Vijaykrishnan Narayanan (DAC, 2016)

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited. - Suman Datta; Alan C. Seabaugh; Michael T. Niemier; Arijit Raychowdhury; Darrell Schlom; Debdeep Jena; Huili Grace Xing; H.-S. Philip Wong; Eric Pop; Sayeef S. Salahuddin; Sumeet Kumar Gupta; Supratik Guha (DAC, 2017)

Full chip power benefits with negative capacitance FETs. - Sandeep Kumar Samal; Sourabh Khandelwal; Asif Islam Khan; Sayeef S. Salahuddin; Chenming Hu; Sung Kyu Lim (ISLPED, 2017)

Combining Learned Representations for Combinatorial Optimization. - Saavan Patel; Sayeef S. Salahuddin (CoRR, 2019)

Negative Capacitance Transistors. - Justin C. Wong; Sayeef S. Salahuddin (Proc. IEEE, 2019)

Reliability of Ferroelectric HfO2-based Memories: From MOS Capacitor to FeFET. - Ava J. Tan; Li-Chen Wang; Yu-Hung Liao; Jong-Ho Bae; Chenming Hu; Sayeef S. Salahuddin (DRC, 2020)

Dynamic Memory and Sequential Logic Design using Negative Capacitance FinFETs. - Ramin Rajaei; Yen-Kai Lin; Sayeef S. Salahuddin; Michael T. Niemier; Xiaobo Sharon Hu (ISCAS, 2020)

GC-eDRAM design using hybrid FinFET/NC-FinFET. - Ramin Rajaei; Yen-Kai Lin; Sayeef S. Salahuddin; Michael T. Niemier; Xiaobo Sharon Hu (ISLPED, 2020)

Logically Synthesized, Hardware-Accelerated, Restricted Boltzmann Machines for Combinatorial Optimization and Integer Factorization. - Saavan Patel; Philip Canoza; Sayeef S. Salahuddin (CoRR, 2020)

Ising Model Optimization Problems on a FPGA Accelerated Restricted Boltzmann Machine. - Saavan Patel; Lili Chen; Philip Canoza; Sayeef S. Salahuddin (CoRR, 2020)

A Density Metric for Semiconductor Technology [Point of View]. - H.-S. Philip Wong; Kerem Akarvardar; Dimitri A. Antoniadis; Jeffrey Bokor; Chenming Hu; Tsu-Jae King Liu; Subhasish Mitra; James D. Plummer; Sayeef S. Salahuddin (Proc. IEEE, 2020)

Scanning the Issue. - H.-S. Philip Wong; Kerem Akarvardar; Dimitri A. Antoniadis; Jeffrey Bokor; Chenming Hu; Tsu-Jae King Liu; Subhasish Mitra; James D. Plummer; Sayeef S. Salahuddin; Lei Deng 003; Xin-Guo Li; Song Han 003; et al. (Proc. IEEE, 2020)

Ultrathin Ferroelectricity and Its Application in Advanced Logic and Memory Devices. - Sayeef S. Salahuddin (IRPS, 2021)

Compact Model for Trap Assisted Tunneling based GIDL. - Chetan K. Dabhi; Girish Pahwa; Sayeef S. Salahuddin; Chenming Hu (DRC, 2022)

On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs. - Nirmaan Shanker; Li-Chen Wang; Suraj S. Cheema; Wenshen Li; Nilotpal Choudhury; Chenming Hu; Souvik Mahapatra; Sayeef S. Salahuddin (VLSI Technology and Circuits, 2022)

Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies. - Richard A. Gottscho; Edlyn V. Levine; Tsu-Jae King Liu; Paul C. McIntyre; Subhasish Mitra; Boris Murmann; Jan M. Rabaey; Sayeef S. Salahuddin; Willy C. Shih; H.-S. Philip Wong (CoRR, 2022)

Record Transconductance in Leff 30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack. - Li-Chen Wang; W. Li; Nirmaan Shanker; Suraj S. Cheema; Shang-Lin Hsu; S. Volkman; U. Sikder; C. Garg; J.-H. Park; Y.-H. Liao; Yen-Kai Lin; Chenming Hu; et al. (VLSI Technology and Circuits, 2023)

FerroX: A GPU-accelerated, 3D phase-field simulation framework for modeling ferroelectric devices. - Prabhat Kumar; Andrew Nonaka; Revathi Jambunathan; Girish Pahwa; Sayeef S. Salahuddin; Zhi Yao (Comput. Phys. Commun., 2023)

PASS: An Asynchronous Probabilistic Processor for Next Generation Intelligence. - Saavan Patel; Philip Canoza; Adhiraj Datar; Steven Lu; Chirag Garg; Sayeef S. Salahuddin (CoRR, 2024)

Efficient Optimization Accelerator Framework for Multistate Ising Problems. - Chirag Garg; Sayeef S. Salahuddin (CoRR, 2025)