Sayeef S. Salahuddin

Orcid: 0000-0002-0315-2208

According to our database¹, Sayeef S. Salahuddin authored at least 26 papers between 2004 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

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PhD thesis

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On csauthors.net:

Bibliography

2023

FerroX: A GPU-accelerated, 3D phase-field simulation framework for modeling ferroelectric devices.

[BibT_eX]

[DOI]

Comput. Phys. Commun., September, 2023

Record Transconductance in Leff~30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies.

[BibT_eX]

[DOI]

CoRR, 2022

On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Compact Model for Trap Assisted Tunneling based GIDL.

[BibT_eX]

[DOI]

Proceedings of the Device Research Conference, 2022

2021

Ultrathin Ferroelectricity and Its Application in Advanced Logic and Memory Devices.

[BibT_eX]

[DOI]

Sayeef S. Salahuddin

Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020

Scanning the Issue.

[BibT_eX]

[DOI]

H.-S. Philip Wong

Kerem Akarvardar

Dimitri A. Antoniadis

Proc. IEEE, 2020

A Density Metric for Semiconductor Technology [Point of View].

[BibT_eX]

[DOI]

H.-S. Philip Wong

Kerem Akarvardar

Dimitri A. Antoniadis

Proc. IEEE, 2020

Ising Model Optimization Problems on a FPGA Accelerated Restricted Boltzmann Machine.

[BibT_eX]

[DOI]

CoRR, 2020

Logically Synthesized, Hardware-Accelerated, Restricted Boltzmann Machines for Combinatorial Optimization and Integer Factorization.

[BibT_eX]

[DOI]

Saavan Patel

Philip Canoza

Sayeef S. Salahuddin

CoRR, 2020

GC-eDRAM design using hybrid FinFET/NC-FinFET.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Dynamic Memory and Sequential Logic Design using Negative Capacitance FinFETs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Reliability of Ferroelectric HfO2-based Memories: From MOS Capacitor to FeFET.

[BibT_eX]

[DOI]

Proceedings of the 2020 Device Research Conference, 2020

2019

Negative Capacitance Transistors.

[BibT_eX]

[DOI]

Justin C. Wong

Sayeef S. Salahuddin

Proc. IEEE, 2019

Combining Learned Representations for Combinatorial Optimization.

[BibT_eX]

[DOI]

Saavan Patel

Sayeef S. Salahuddin

CoRR, 2019

2017

Full chip power benefits with negative capacitance FETs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Nonvolatile memory design based on ferroelectric FETs.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Proceedings of the 53rd Annual Design Automation Conference, 2016

2013

Electrothermal analysis of spin-transfer-torque random access memory arrays.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

2011

Performance assessment of partially unzipped carbon nanotube field-effect transistors.

[BibT_eX]

[DOI]

Youngki Yoon

Sayeef S. Salahuddin

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

2010

Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes.

[BibT_eX]

[DOI]

Subho Chatterjee

Sayeef S. Salahuddin

Saibal Mukhopadhyay

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2008

Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2004

Reducing signal-bias from MAD estimated noise level for DCT speech enhancement.

[BibT_eX]

[DOI]

Md. Kamrul Hasan

Sayeef S. Salahuddin

M. Rezwan Khan

Signal Process., 2004

Sayeef S. Salahuddin

Timeline

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