Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style. - Tooraj Nikoubin; Mahdieh Grailoo; Sayyed Hasan Mozafari (J. Low Power Electron., 2010)

A Low Cost circuit level fault detection technique to Full Adder design. - Sayyed Hasan Mozafari; Mahdi Fazeli; Shaahin Hessabi; Seyed Ghassem Miremadi (ICECS, 2011)

Heterogeneous redundancy to address performance and cost in multi-core SIMT: work-in-progress. - M. Naghashi; Sayyed Hasan Mozafari; Shaahin Hessabi (CODES+ISSS, 2017)