A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC. - Howard L. Kalter; Charles H. Stapper; John E. Barth Jr.; John DiLorenzo; Charles E. Drake; John A. Fifield; Gordon A. Kelley; Scott C. Lewis; Willem B. van der Hoeven; James A. Yankosky (IEEE J. Solid State Circuits, 1990)

A 256-Mcell Phase-Change Memory Chip Operating at 2+ Bit/Cell. - Gael F. Close; Urs Frey; Jack Morrish; Richard Jordan; Scott C. Lewis; Tom Maffitt; M. J. BrightSky; Christoph Hagleitner; Chung Hon Lam; Evangelos Eleftheriou (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory. - Pritish Narayanan; Alessandro Fumarola; Lucas L. Sanches; Kohji Hosokawa; Scott C. Lewis; Robert M. Shelby; Geoffrey W. Burr (IBM J. Res. Dev., 2017)

AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed. - Hung-Yang Chang; Pritish Narayanan; Scott C. Lewis; Nathan C. P. Farinha; Kohji Hosokawa; Charles Mackin; Hsinyu Tsai; Stefano Ambrogio; An Chen 002; Geoffrey W. Burr (IBM J. Res. Dev., 2019)

Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited). - Kohji Hosokawa; Pritish Narayanan; Stefano Ambrogio; Hsinyu Tsai; Charles Mackin; Andrea Fasoli; Alexander M. Friz; An Chen 002; Jose Luquin; Katherine Spoon; Geoffrey W. Burr; Scott C. Lewis (ISCAS, 2021)