Delay-insensitive gate-level pipelining. - Scott C. Smith; Ronald F. DeMara; Jiann-Shiun Yuan; M. Hagedorn; Dennis Ferguson (Integr., 2001)

Speedup of Self-Timed Digital Systems Using Early Completion. - Scott C. Smith (ISVLSI, 2002)

NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation. - Scott C. Smith; Ronald F. DeMara; Jiann-Shiun Yuan; M. Hagedorn; Dennis Ferguson (J. Syst. Archit., 2002)

On generating random systems: a gramian approach. - Scott C. Smith; James Fisher (ACC, 2003)

Design and Characterization of NULL Convention Arithmetic Logic Units. - Satish K. Bandapati; Scott C. Smith (VLSI, 2003)

Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy. - Scott C. Smith (VLSI, 2003)

Design and Characterization of Null Convention Self-Timed Multipliers. - Satish K. Bandapati; Scott C. Smith; Minsu Choi (IEEE Des. Test Comput., 2003)

Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput. - Scott C. Smith (ESA/VLSI, 2004)

Design of a NULL Convention Self-Timed Divider. - Scott C. Smith (ESA/VLSI, 2004)

Optimization of NULL convention self-timed circuits. - Scott C. Smith; Ronald F. DeMara; Jiann-Shiun Yuan; Dennis Ferguson; D. Lamb (Integr., 2004)

Implementation of Design For Test for Asynchronous NCL Designs. - Bonita Bhaskaran; Venkat Satagopan; Waleed K. Al-Assadi; Scott C. Smith (CDES, 2005)

High-Speed Energy Estimation for Delay-Insensitive Circuits. - Bonita Bhaskaran; Venkat Satagopan; Scott C. Smith (CDES, 2005)

Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation. - Anshul Singh; Scott C. Smith (CDES, 2005)

Development of a large word-width high-speed asynchronous multiply and accumulate unit. - Scott C. Smith (Integr., 2005)

Speedup of NULL convention digital circuits using NULL cycle reduction. - Scott C. Smith (J. Syst. Archit., 2006)

Design of a logic element for implementing an asynchronous FPGA. - Scott C. Smith (FPGA, 2007)

Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits. - Ganesh K. Venayagamoorthy; Scott C. Smith; Gaurav Singhal (Eng. Appl. Artif. Intell., 2007)

Automated energy calculation and estimation for delay-insensitive digital circuits. - Venkat Satagopan; Bonita Bhaskaran; Anshul Singh; Scott C. Smith (Microelectron. J., 2007)

DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. - Venkat Satagopan; Bonita Bhaskaran; Waleed K. Al-Assadi; Scott C. Smith; Sindhu Kakarla (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. - Scott C. Smith (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power. - Andrew Bailey; Ahmad Al Zahrani; Guoyuan Fu; Jia Di; Scott C. Smith (J. Low Power Electron., 2008)

Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. - Brent Hollosi; Tao Zhang 032; Ravi Sankar Parameswaran Nair; Yuan Xie 001; Jia Di; Scott C. Smith (3DIC, 2009)

Delay-Insensitive Ternary Logic. - Ravi Sankar Parameswaran Nair; Scott C. Smith; Jia Di (CDES, 2009)

Particle Swarm Optimization: A Hardware Implementation. - Parviz Palangpour; Ganesh K. Venayagamoorthy; Scott C. Smith (CDES, 2009)

Integrated software-hardware design for ultra-low power infrastructure monitoring. - Jingxian Wu 001; Scott C. Smith (ITSC, 2009)

Designing Asynchronous Circuits using NULL Convention Logic (NCL) - Scott C. Smith; Jia Di (Morgan & Claypool Publishers, 2009)

Delay-Insensitive Cell Matrix. - Scott C. Smith; David Roclin; Jia Di (CDES, 2010)

Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum. - Scott C. Smith; Waleed K. Al-Assadi; Jia Di (IEEE Trans. Educ., 2010)

Uncle - An RTL Approach to Asynchronous Design. - Robert B. Reese; Scott C. Smith; Mitchell A. Thornton (ASYNC, 2012)

CMOS implementation comparison of NCL gates. - Farhad Alibeygi Parsan; Scott C. Smith (MWSCAS, 2012)

CMOS implementation of static threshold gates with hysteresis: A new approach. - Farhad Alibeygi Parsan; Scott C. Smith (VLSI-SoC, 2012)

CMOS Implementation of Threshold Gates with Hysteresis. - Farhad Alibeygi Parsan; Scott C. Smith (VLSI-SoC (Selected Papers), 2012)

Sleep Convention Logic using partially slept function blocks. - Parviz Palangpour; Scott C. Smith (MWSCAS, 2013)

Quantum-dot cellular automaton of asynchronous Null Convention Logic multiplier design. - Pragadesh Varadharajan; Waleed K. Al-Assadi; Shabab F. Alam; Scott C. Smith (MWSCAS, 2013)

An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency. - Michael Hinds; Brett Sparkman; Jia Di; Scott C. Smith (J. Low Power Electron., 2013)

Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic. - Washington Cilio; Michael Linder; Chris Porter; Jia Di; Dale R. Thompson; Scott C. Smith (Microelectron. J., 2013)

Equivalence verification for NULL Convention Logic (NCL) circuits. - Vidura Wijayasekara; Sudarshan K. Srinivasan; Scott C. Smith (ICCD, 2014)

SCL design of a pipelined 8051 ALU. - Farhad Alibeygi Parsan; J. Zhao; Scott C. Smith (MWSCAS, 2014)

Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits. - Farhad Alibeygi Parsan; Waleed K. Al-Assadi; Scott C. Smith (IEEE Trans. Very Large Scale Integr. Syst., 2014)

An FPGA-based design for joint control and monitoring of permanent magnet synchronous motors. - Paul Rogers; Rajesh Kavasseri; Scott C. Smith (ReConFig, 2016)

Design for Testability of Sleep Convention Logic. - Farhad Alibeygi Parsan; Scott C. Smith; Waleed K. Al-Assadi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Formal modeling and verification for pre-charge half buffer gates and circuits. - Ashiq A. Sakib; Scott C. Smith; Sudarshan K. Srinivasan (MWSCAS, 2017)

Analysis and design of CMOS resettable C-elements. - Nasim Soufizadeh-Balaneji; Scott C. Smith (MWSCAS, 2017)

An FPGA-in-the-loop approach for HDL motor controller verification. - Paul Rogers; Rajesh Kavasseri; Scott C. Smith (ReConFig, 2017)

An Equivalence Verification Methodology for Combinational Asynchronous PCHB Circuits. - Ashiq A. Sakib; Scott C. Smith; Sudarshan K. Srinivasan (MWSCAS, 2018)

An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits. - Mousam Hossain; Ashiq A. Sakib; Sudarshan K. Srinivasan; Scott C. Smith (ISCAS, 2019)

Formal Modeling and Verification of PCHB Asynchronous Circuits. - Ashiq A. Sakib; Scott C. Smith; Sudarshan K. Srinivasan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Hardware Trojan Design and Detection in Asynchronous NCL Circuits. - Kushal K. Ponugoti; Sudarshan K. Srinivasan; Scott C. Smith (ICECS, 2020)

Implementation of Static NCL Threshold Gates Using Emerging CNTFET Technology. - Ashiq A. Sakib; Scott C. Smith (ICECS, 2020)

Further Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit. - Nauman Jalil; Scott C. Smith (MWSCAS, 2020)

Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits. - Son N. Le; Sudarshan K. Srinivasan; Scott C. Smith (MWSCAS, 2020)

Formal Verification of Completion-Completeness for NCL Circuits. - Son N. Le; Sudarshan K. Srinivasan; Scott C. Smith (MWSCAS, 2020)

Implementation of FinFET Based Static NCL Threshold Gates: An Analysis of Design Choice. - Ashiq A. Sakib; Abir A. Akib; Scott C. Smith (MWSCAS, 2020)

Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits. - Brett Sparkman; Scott C. Smith; Jia Di (VTS, 2020)

Performance optimization of rotation-tolerant Viola-Jones-based blackbird detection. - Nauman Jalil; Scott C. Smith; Roger Green (J. Real Time Image Process., 2020)

An Ancillary Services Model for Data Centers and Power Systems. - Sahibzada Muhammad Ali; Muhammad Jawad 001; Muhammad Usman Shahid Khan; Kashif Bilal; Jacob Glower; Scott C. Smith; Samee U. Khan; Keqin Li 001; Albert Y. Zomaya (IEEE Trans. Cloud Comput., 2020)

Security Threat Modeling for Power Transformers in Cyber-Physical Environments. - BoHyun Ahn; Taesic Kim; Scott C. Smith; Young-Woo Youn; Myung-Hyo Ryu (ISGT, 2021)

Memristor-Based Variation-Enabled Differentially Private Learning Systems for Edge Computing in IoT. - Jingyan Fu; Zhiheng Liao; Jianqing Liu; Scott C. Smith; Jinhui Wang (IEEE Internet Things J., 2021)

Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation. - Hritom Das; Ali Ahmad Haidous; Scott C. Smith; Na Gong (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism. - Brett Sparkman; Scott C. Smith; Jia Di (J. Electron. Test., 2022)

Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits. - Kushal K. Ponugoti; Sudarshan K. Srinivasan; Scott C. Smith; Nimish Mathure (IET Comput. Digit. Tech., 2022)

Approximate Memory for Low-Power Video Applications. - Hritom Das; Ali Ahmad Haidous; Scott C. Smith; Na Gong (IEEE Access, 2023)

Combining Relaxation With NCL_X for Enhanced Optimization of Asynchronous Null Convention Logic Circuits. - Danylo Khodosevych; Alexander C. Bodoh; Ashiq A. Sakib; Scott C. Smith (IEEE Access, 2023)