A PRML read/write channel IC using analog signal processing for 200 Mb/s HDD. - Kavch Parsi; Robert P. Burns; Alan Chaiken; Mark Chambers; William R. Forni; David Harnishfeger; Scott Kaylor; Micheal J. Pennell; Jose O. Perez; Narendra Rao; Mark Rohrhaugh; Mike Ross; et al. (IEEE J. Solid State Circuits, 1996)

A 16b 100-to-160MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDR. - Robert Payne; Marco Corsi; David Smith; Scott Kaylor; Daniel Hsieh (ISSCC, 2010)

A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR. - Robert Payne; Marco Corsi; David Smith; Tien-Ling Hsieh; Scott Kaylor (IEEE J. Solid State Circuits, 2010)

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC. - Manar El-Chammas; Xiaopeng Li; Shigenobu Kimura; Kenneth Maclean; Jake Hu; Mark Weaver; Matthew Gindlesperger; Scott Kaylor; Robert Payne; Charles K. Sestok; William Bright (IEEE J. Solid State Circuits, 2014)

9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth. - Nikolaus Klemmer; Siraj Akhtar; Venkatesh Srinivasan; Petteri Litmanen; Himanshu Arora; Satish Uppathil; Scott Kaylor; A. Akour; Victoria Wang; Mounir Fares; F. Dulger; A. Frank; et al. (ISSCC, 2016)

A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz. - Vishnu Ravinuthula; William Bright; Mark Weaver; Kenneth Maclean; Scott Kaylor; Sidharth Balasubramanian; Jesse Coulon; Robert Keller; Bao Nguyen; Ebenezer Dwobeng (VLSI Circuits, 2016)