A High-Speed Optical Multi-Drop Bus for Computer Interconnections. - Michael R. T. Tan; Paul Rosenberg; Jong Souk Yeo; Moray McLaren; Sagi Mathai; Terry Morris; Joseph Straznicky; Norman P. Jouppi; Huei Pei Kuo; Shih-Yuan Wang; Scott Lerner; Pavel Kornilovich; et al. (Hot Interconnects, 2008)

Timing characterization of clock buffers for clock tree synthesis. - Can Sitik; Scott Lerner; Baris Taskin (ICCD, 2014)

Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation. - Siddharth Nilakantan; Scott Lerner; Mark Hempstead; Baris Taskin (VLSID, 2015)

Stability of Rotary Traveling Wave Oscillators under process variations and NBTI. - Ragh Kuttappa; Leo Filippini; Scott Lerner; Baris Taskin (ISCAS, 2017)

Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors. - Scott Lerner; Baris Taskin (ISQED, 2017)

WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS. - Scott Lerner; Baris Taskin (ISVLSI, 2017)

Slew-down: analysis of slew relaxation for low-impact clock buffers. - Scott Lerner; Eric Leggett; Baris Taskin (SLIP, 2017)

Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis. - Scott Lerner; Baris Taskin (IGSC, 2018)

NoC Router Lifetime Improvement using Per-Port Router Utilization. - Scott Lerner; Vasil Pano; Baris Taskin (ISCAS, 2018)

Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement. - Vasil Pano; Scott Lerner; Isikcan Yilmaz; Michael Lui; Baris Taskin (ISCAS, 2018)

Low Swing - Low Frequency Rotary Traveling Wave Oscillators. - Ragh Kuttappa; Scott Lerner; Leo Filippini; Baris Taskin (ISCAS, 2019)

Robust Low Power Clock Synchronization for Multi-Die Systems. - Ragh Kuttappa; Baris Taskin; Scott Lerner; Vasil Pano; Ioannis Savidis (ISLPED, 2019)

Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. - Scott Lerner; Baris Taskin (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. - Scott Lerner; Isikcan Yilmaz; Baris Taskin (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems. - Ragh Kuttappa; Baris Taskin; Scott Lerner; Vasil Pano (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Design Automation for Charge Recovery Logic. - Yilmaz Ege Gonul; Leo Filippini; Junghoon Oh; Ragh Kuttappa; Scott Lerner; Mineo Kaneko; Baris Taskin (ISCAS, 2024)