Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology. - Syed M. Alam; Robert E. Jones; Scott Pozder; Ankur Jain (ISQED, 2009)

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits. - Ioannis Savidis; Syed M. Alam; Ankur Jain; Scott Pozder; Robert E. Jones; Ritwik Chatterjee (Microelectron. J., 2010)

Interstratum Connection Design Considerations for Cost-Effective 3-D System Integration. - Syed M. Alam; Robert E. Jones; Scott Pozder; Ritwik Chatterjee; Shahid Rauf; Ankur Jain (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints. - Ankur Jain; Syed M. Alam; Scott Pozder; Robert E. Jones (IET Comput. Digit. Tech., 2011)

A Comparison of Environmental Stressing Data and Simulation at the Corner of a Test Chip in a FC-BGA Package. - Sandeep Mallampati; Zaeem Baig; Scott Pozder; Eng Chye Chua (IRPS, 2019)