Programming Approach for Fuzzy Model-Based Multiobjective Control Systems. - Zeungnam Bien; Dong-oh Kang; Se-Hyun Yang (Int. J. Uncertain. Fuzziness Knowl. Based Syst., 1999)

Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories - Michael D. Powell; Se-Hyun Yang; Babak Falsafi; Kaushik Roy 001; T. N. Vijaykumar (ISLPED, 2000)

An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. - Se-Hyun Yang; Michael D. Powell; Babak Falsafi; Kaushik Roy 001; T. N. Vijaykumar (HPCA, 2001)

Reducing leakage in a high-performance deep-submicron instruction cache. - Michael D. Powell; Se-Hyun Yang; Babak Falsafi; Kaushik Roy 001; T. N. Vijaykumar (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. - Se-Hyun Yang; Michael D. Powell; Babak Falsafi; T. N. Vijaykumar (HPCA, 2002)

Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches. - Se-Hyun Yang; Babak Falsafi (MICRO, 2003)

Accurate and Complexity-Effective Spatial Pattern Prediction. - Chi F. Chen; Se-Hyun Yang; Babak Falsafi; Andreas Moshovos (HPCA, 2004)

Session 10 overview: High-performance digital: High performance digital subcommittee. - Lew Chua-Eoan; Se-Hyun Yang (ISSCC, 2012)

A 32nm high-k metal gate application processor with GHz multi-core CPU. - Se-Hyun Yang; Seogjun Lee; Jae Young Lee; Jeonglae Cho; Hoi-Jin Lee; Dongsik Cho; Junghun Heo; Sunghoon Cho; Youngmin Shin; Sunghee Yun; Euiseok Kim; Ukrae Cho; et al. (ISSCC, 2012)

Session 3 overview: Processors. - Se-Hyun Yang; Eric Fluhr (ISSCC, 2013)

A 1.6 GHz quad-core application processor manufactured in 32 nm high-k metal gate process for smart mobile devices. - Se-Hyun Yang; Jungyul Pyo; Youngmin Shin; Jae Cheol Son (IEEE Commun. Mag., 2013)

F3: Adaptive design techniques for energy efficiency. - Eric Fluhr; Michael Polley; Se-Hyun Yang; Vasantha Erraguntla; Tobias Noll; Kees van Berkel 001 (ISSCC, 2014)