One chip-low power digital-TCXO with sub-ppm accuracy. - Se-Joong Lee; Jinho Han; Seung-Ho Hank; Joe-Ho Lee; Jung-Su Kim; Minkyu Je; Hoi-Jun Yoo (ISCAS, 2000)

A 670 ps, 64 bit dynamic low-power adder design. - Ramchan Woo; Se-Joong Lee; Hoi-Jun Yoo (ISCAS, 2000)

An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications. - Chi Weon Yoon; Ramchan Woo; Jeengheon Kook; Se-Joong Lee; Kangmin Lee; Hoi-Jun Yeo (IEEE J. Solid State Circuits, 2001)

A practical method to use eDRAM in the shared bus packet switch. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (GLOBECOM, 2002)

Race logic architecture (RALA): a novel logic concept using the race scheme of input variables. - Se-Joong Lee; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2002)

A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth. - Se-Jeong Park; Jeong-Su Kim; Ramchan Woo; Se-Joong Lee; Kang-Min Lee; Tae-Hum Yang; Jin-Yong Jung; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2002)

A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip. - Ramchan Woo; Chi Weon Yoon; Jeonghoon Kook; Se-Joong Lee; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2002)

A distributed crossbar switch scheduler for on-chip networks. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (CICC, 2003)

A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (ESSCIRC, 2003)

A 10Gbps/port 8×8 shared bus switch with embedded DRAM hierarchical output buffer. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (ESSCIRC, 2003)

SILENT: serialized low energy transmission coding for on-chip interconnection networks. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (ICCAD, 2004)

On-chip network based embedded core testing. - Jong-Sun Kim; Min-Su Hwang; Seungsu Roh; Ja-Young Lee; Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (SoCC, 2004)

Low energy transmission coding for on-chip serial communications. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (SoCC, 2004)

An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip. - Kwanho Kim; Se-Joong Lee; Kangmin Lee; Hoi-Jun Yoo (ISCAS (3), 2005)

A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip. - Donghyun Kim; Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (ISCAS (3), 2005)

Analysis and Implementation of Practical, Cost-Effective Networks on Chips. - Se-Joong Lee; Kangmin Lee; Hoi-Jun Yoo (IEEE Des. Test Comput., 2005)

Packet-switched on-chip interconnection network for system-on-chip applications. - Se-Joong Lee; Kangmin Lee; Seong-Jun Song; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes. - Se-Joong Lee; Kwanho Kim; Hyejung Kim; Namjun Cho; Hoi-Jun Yoo (DATE, 2006)

Low-power network-on-chip for high-performance SoC design. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (IEEE Trans. Very Large Scale Integr. Syst., 2006)

81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC. - Donghyun Kim 014; Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Se-Joong Lee; Hoi-Jun Yoo (IEEE Trans. Very Large Scale Integr. Syst., 2009)