Design of a high-density SoC FPGA at 20nm. - Brad Vest; Sean Atsatt; Mike Hutton (Hot Chips Symposium, 2014)

Arria™ 10 device architecture. - Jeffrey Tyhach; Mike Hutton; Sean Atsatt; Arifur Rahman; Brad Vest; David M. Lewis; Martin Langhammer; Sergey Y. Shumarayev; Tim Hoang; Allen Chan; Dong-Myung Choi; Dan Oh; et al. (CICC, 2015)

Sectors: Divide & Conquer and Softwarization in the Design and Validation of the Stratix® 10 FPGA. - Dana L. How; Sean Atsatt (FCCM, 2016)

3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration. - David Greenhill; Ron Ho; David M. Lewis; Herman Schmit; Kok Hong Chan; Andy Tong; Sean Atsatt; Dana How; Peter McElheny; Keith Duwel; Jeffrey Schulz; Darren Faulkner; et al. (ISSCC, 2017)