A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery. - Mike Harwood; Nirmal Warke; Richard Simpson 004; Tom Leslie; Ajith Amerasekera; Sean Batty; Derek Colman; Eugenia Carr; Venu Gopinathan; Steve Hubbins; Peter Hunt; Andy Joy; et al. (ISSCC, 2007)

A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications. - Mike Harwood; Steffen Nielsen; Andre Szczepanek; Richard Allred; Sean Batty; Mike Case; Simon Forey; Karthik Gopalakrishnan; Larry Kan; Bob Killips; Parmanand Mishra; Rohit Pande; et al. (ISSCC, 2012)