Managing Don't Cares in Boolean Satisfiability. - Sean Safarpour; Andreas G. Veneris; Rolf Drechsler; Joanne Lee (DATE, 2004)

Debugging sequential circuits using Boolean satisfiability. - Moayad Fahim Ali; Andreas G. Veneris; Alexander Smith 001; Sean Safarpour; Rolf Drechsler; Magdy S. Abadir (ICCAD, 2004)

Diagnosing multiple transition faults in the absence of timing information. - Jiang Brandon Liu; Magdy S. Abadir; Andreas G. Veneris; Sean Safarpour (ACM Great Lakes Symposium on VLSI, 2005)

Utilizing don't care states in SAT-based bounded sequential problems. - Sean Safarpour; Görschwin Fey; Andreas G. Veneris; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2005)

Post-verification debugging of hierarchical designs. - Moayad Fahim Ali; Sean Safarpour; Andreas G. Veneris; Magdy S. Abadir; Rolf Drechsler (ICCAD, 2005)

Efficient SAT-based Boolean matching for FPGA technology mapping. - Sean Safarpour; Andreas G. Veneris; Gregg Baeckler; Richard Yuan (DAC, 2006)

On the relation between simulation-based and SAT-based diagnosis. - Görschwin Fey; Sean Safarpour; Andreas G. Veneris; Rolf Drechsler (DATE, 2006)

Integrating observability don't cares in all-solution SAT solvers. - Sean Safarpour; Andreas G. Veneris; Rolf Drechsler (ISCAS, 2006)

Abstraction and Refinement Techniques in Automated Design Debugging. - Sean Safarpour; Andreas G. Veneris (MTV, 2006)

Trace Compaction using SAT-based Reachability Analysis. - Sean Safarpour; Andreas G. Veneris; Hratch Mangassarian (ASP-DAC, 2007)

Maximum circuit activity estimation using pseudo-boolean satisfiability. - Hratch Mangassarian; Andreas G. Veneris; Sean Safarpour; Farid N. Najm; Magdy S. Abadir (DATE, 2007)

Improved Design Debugging Using Maximum Satisfiability. - Sean Safarpour; Hratch Mangassarian; Andreas G. Veneris; Mark H. Liffiton; Karem A. Sakallah (FMCAD, 2007)

A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. - Hratch Mangassarian; Andreas G. Veneris; Sean Safarpour; Marco Benedetti; Duncan Exon Smith (ICCAD, 2007)

Improved SAT-based Reachability Analysis with Observability Don't Cares. - Sean Safarpour; Andreas G. Veneris; Rolf Drechsler (J. Satisf. Boolean Model. Comput., 2008)

The day Sherlock Holmes decided to do EDA. - Andreas G. Veneris; Sean Safarpour (DAC, 2009)

Towards automated ECOs in FPGAs. - Andrew C. Ling; Stephen Dean Brown; Jianwen Zhu; Sean Safarpour (FPGA, 2009)

Spatial and temporal design debug using partial MaxSAT. - Yibin Chen; Sean Safarpour; Andreas G. Veneris; João Marques-Silva 001 (ACM Great Lakes Symposium on VLSI, 2009)

Automated debugging with high level abstraction and refinement. - Sean Safarpour; Andreas G. Veneris (HLDVT, 2009)

Automated Design Debugging With Abstraction and Refinement. - Sean Safarpour; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Managing verification error traces with bounded model debugging. - Sean Safarpour; Andreas G. Veneris; Farid N. Najm (ASP-DAC, 2010)

Automated silicon debug data analysis techniques for a hardware data acquisition environment. - Yu-Shen Yang; Brian Keng; Nicola Nicolici; Andreas G. Veneris; Sean Safarpour (ISQED, 2010)

An Automated Framework for Correction and Debug of PSL Assertions. - Brian Keng; Andreas G. Veneris; Sean Safarpour (MTV, 2010)

Automated Design Debugging With Maximum Satisfiability. - Yibin Chen; Sean Safarpour; João Marques-Silva 001; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Bounded Model Debugging. - Brian Keng; Sean Safarpour; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

From RTL to silicon: The case for automated debug. - Andreas G. Veneris; Brian Keng; Sean Safarpour (ASP-DAC, 2011)

Automated debugging of SystemVerilog assertions. - Brian Keng; Sean Safarpour; Andreas G. Veneris (DATE, 2011)

Debugging with dominance: On-the-fly RTL debug solution implications. - Hratch Mangassarian; Andreas G. Veneris; Duncan Exon Smith; Sean Safarpour (ICCAD, 2011)

Toward Automated ECOs in FPGAs. - Andrew C. Ling; Stephen Dean Brown; Sean Safarpour; Jianwen Zhu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)