Wire sizing with scattering effect for nanoscale interconnection. - Sean X. Shi; David Z. Pan (ASP-DAC, 2006)

Process variation aware OPC with variational lithography modeling. - Peng Yu; Sean X. Shi; David Z. Pan (DAC, 2006)

A unified non-rectangular device and circuit simulation model for timing and power. - Sean X. Shi; Peng Yu; David Z. Pan (ICCAD, 2006)

Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. - Ashutosh Chakraborty; Sean X. Shi; David Z. Pan (DATE, 2008)

Latch Modeling for Statistical Timing Analysis. - Sean X. Shi; Anand Ramalingam; Daifeng Wang; David Z. Pan (DATE, 2008)

Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement. - Ashutosh Chakraborty; Sean X. Shi; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)