The vector fixed point unit of the synergistic processor element of the cell architecture processor. - Nicolas Mäding; Jens Leenstra; Jürgen Pille; Rolf Sautter; Stefan Büttner; Sebastian Ehrenreich; W. Haller (ESSCIRC, 2005)

Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V. - Jürgen Pille; Chad Adams; Todd Christensen; Scott R. Cottier; Sebastian Ehrenreich; Fumihiro Kono; Daniel Nelson; Osamu Takahashi; Shunsako Tokito; Otto A. Torreiter; Otto Wagner; Dieter F. Wendel (ISSCC, 2007)

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V. - Juergen Pille; Chad Adams; Todd Christensen; Scott R. Cottier; Sebastian Ehrenreich; Fumihiro Kono; Daniel Nelson; Osamu Takahashi; Shunsako Tokito; Otto A. Torreiter; Otto Wagner; Dieter F. Wendel (IEEE J. Solid State Circuits, 2008)

A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. - Gary S. Ditlow; Robert K. Montoye; Salvatore N. Storino; Sherman M. Dance; Sebastian Ehrenreich; Bruce M. Fleischer; Thomas W. Fox; Kyle M. Holmes; Junichi Mihara; Yutaka Nakamura; Shohji Onishi; Robert Shearer; et al. (ISSCC, 2011)