Wide swing signal amplification by SC voltage doubling. - Sebastian Höppner; René Schüffny; Zuo-Min Tsai; Huei Wang (ISCAS, 2010)

A low-power cell-based-design multi-port register file in 65nm CMOS technology. - Johannes Uhlig; Sebastian Höppner; Georg Ellguth; René Schüffny (ISCAS, 2010)

Efficient compensation of delay variations in high-speed network-on-chip data links. - Sebastian Höppner; Dennis Walter; Holger Eisenreich; René Schüffny (SoC, 2010)

Strategies for initial sizing and operating point analysis of analog circuits. - Volker Boos; Jacek Nowak; Matthias Sylvester; Stephan Henker; Sebastian Höppner; Heiko Grimm; Dominik Krausse; Ralf Sommer (DATE, 2011)

Mismatch characterization of high-speed NoC links using asynchronous sub-sampling. - Sebastian Höppner; Dennis Walter; Georg Ellguth; René Schüffny (SoC, 2011)

A power management architecture for fast per-core DVFS in heterogeneous MPSoCs. - Sebastian Höppner; Chenming Shao; Holger Eisenreich; Georg Ellguth; Mario Ander; René Schüffny (ISCAS, 2012)

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. - Dennis Walter; Sebastian Höppner; Holger Eisenreich; Georg Ellguth; Stephan Henker; Stefan Hänzsche; René Schüffny; Markus Winter 002; Gerhard P. Fettweis (ISSCC, 2012)

A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates. - Markus Winter 002; Steffen Kunze; Esther P. Adeva; Björn Mennenga; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Sebastian Höppner; Stefan Scholze; René Schüffny; Tomoyoshi Kobori (ISSCC, 2012)

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links. - Sebastian Höppner; Dennis Walter; Georg Ellguth; René Schüffny (Int. J. Embed. Real Time Commun. Syst., 2012)

A 32 GBit/s communication SoC for a waferscale neuromorphic system. - Stefan Scholze; Holger Eisenreich; Sebastian Höppner; Georg Ellguth; Stephan Henker; Mario Ander; Stefan Hänzsche; Johannes Partzsch; Christian Mayr 001; René Schüffny (Integr., 2012)

Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology. - Sebastian Höppner; Dennis Walter; Holger Eisenreich; Stefan Schiefer; René Schüffny (ECCTD, 2013)

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology. - Sebastian Höppner; Stefan Hänzsche; Georg Ellguth; Dennis Walter; Holger Eisenreich; René Schüffny (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology. - Sebastian Höppner; Holger Eisenreich; Stephan Henker; Dennis Walter; Georg Ellguth; René Schüffny (IEEE Trans. Very Large Scale Integr. Syst., 2013)

An energy efficient multi-bit TSV transmitter using capacitive coupling. - Johannes Gorner; Sebastian Höppner; Dennis Walter; Michael Haas; Dirk Plettemeier; René Schüffny (ICECS, 2014)

A compact on-chip IR-drop measurement system in 28 nm CMOS technology. - Sebastian Dietel; Sebastian Höppner; Holger Eisenreich; Georg Ellguth; Stefan Hänzsche; Stephan Henker; René Schüffny; Tim Brauninger; Ulrich Fiedler (ISCAS, 2014)

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. - Benedikt Noethen; Oliver Arnold; Esther P. Adeva; Tobias Seifert; Erik Fischer; Steffen Kunze; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Stephan Hartmann 002; Sebastian Höppner; et al. (ISSCC, 2014)

A 10 bit 16 MS/s redundant SAR ADC with flexible window function for a digitally controlled DC-DC converter in 28 nm CMOS. - Stefan Hänzsche; Sebastian Höppner; René Schüffny (NORCHIP, 2014)

Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS. - Marko Noack; Johannes Partzsch; Christian Mayr 001; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Georg Ellguth; René Schüffny (CoRR, 2014)

A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology. - Stefan Hänzsche; Sebastian Höppner; Georg Ellguth; René Schüffny (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An all-digital PWM generator with 62.5ps resolution in 28nm CMOS technology. - Sebastian Höppner; Stefan Hänzsche; Stefan Scholze; René Schüffny (ISCAS, 2015)

A deep-submicron CMOS flow for general-purpose timing-detection insertion. - Andreas Dixius; Dennis Walter; Sebastian Höppner; Holger Eisenreich; René Schüffny (MIXDES, 2015)

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. - Sebastian Höppner; Dennis Walter; Thomas Hocker; Stephan Henker; Stefan Hänzsche; Daniel Sausner; Georg Ellguth; Jens-Uwe Schluessler; Holger Eisenreich; René Schüffny (IEEE J. Solid State Circuits, 2015)

An MPSoC for energy-efficient database query processing. - Sebastian Haas; Oliver Arnold; Benedikt Nöthen; Stefan Scholze; Georg Ellguth; Andreas Dixius; Sebastian Höppner; Stefan Schiefer; Stephan Hartmann 002; Stephan Henker; Thomas Hocker; Jörg Schreiter; et al. (DAC, 2016)

A database accelerator for energy-efficient query processing and optimization. - Sebastian Haas; Oliver Arnold; Stefan Scholze; Sebastian Höppner; Georg Ellguth; Andreas Dixius; Annett Ungethüm; Eric Mier; Benedikt Noethen; Emil Matús; Stefan Schiefer; Love Cederstroem; et al. (NORCAS, 2016)

True random number generation from bang-bang ADPLL jitter. - Felix Neumärker; Sebastian Höppner; Andreas Dixius; Christian Mayr 001 (NORCAS, 2016)

A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits. - Christian Mayr 001; Johannes Partzsch; Marko Noack; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Georg Ellguth; René Schüffny (IEEE Trans. Biomed. Circuits Syst., 2016)

A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring. - Sebastian Höppner; Johannes Partzsch; Johannes Neumann; René Schüffny; Christian Mayr 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. - Sebastian Haas; Tobias Seifert; Benedikt Nöthen; Stefan Scholze; Sebastian Höppner; Andreas Dixius; Esther Pérez Adeva; Thomas R. Augustin; Friedrich Pauls; Sadia Moriam; Mattis Hasler; Erik Fischer; et al. (DAC, 2017)

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Prateek Joshi; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; et al. (ISCAS, 2017)

Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; Matthias Eberlein; et al. (ISCAS, 2017)

A fixed point exponential function accelerator for a neuromorphic many-core system. - Johannes Partzsch; Sebastian Höppner; Matthias Eberlein; René Schüffny; Christian Mayr 001; David R. Lester; Steve B. Furber (ISCAS, 2017)

Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology. - Heiner Bauer; Sebastian Höppner; Johannes Partzsch; Dennis Walter; Christian Mayr 001; Florian Schraut; Holger Eisenreich (NORCAS, 2017)

Application-specific architectures for energy-efficient database query processing and optimization. - Sebastian Haas; Stefan Scholze; Sebastian Höppner; Annett Ungethüm; Christian Mayr 001; René Schüffny; Wolfgang Lehner; Gerhard P. Fettweis (Microprocess. Microsystems, 2017)

Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip. - Mantas Mikaitis; David R. Lester; Delong Shang; Steve B. Furber; Gengting Liu; Jim D. Garside; Stefan Scholze; Sebastian Höppner; Andreas Dixius (ARITH, 2018)

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC. - Sebastian Höppner; Jörg Schreiter; Robert Niebsch; Stephan Scherzer; Ulrich Hensel; Jörg Winkler; Mario Orgis; Holger Eisenreich; Dennis Walter; Uwe Steeb; André Scharfe; Clifford Dmello; et al. (ESSDERC, 2019)

Hard Real-Time Capable OPC UA Server as Hardware Peripheral for Single Chip IoT Systems. - Chris Paul Iatrou; Heiner Bauer; Markus Graube; Sebastian Höppner; Julian Rahm; Leon Urbas (ETFA, 2019)

A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology. - Florian Schraut; Holger Eisenreich; Sebastian Höppner; Christian Mayr 001 (ISCAS, 2019)

A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration. - Franz Marcus Schüffny; Sebastian Höppner; Alexander Oefelein; Christian Mayr 001 (ISCAS, 2019)

Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS. - Florian Protze; Martin Kreißig; Frank Ellinger; Sebastian Höppner; Stephan Hartmann 002; Stefan Hänzsche; Stefan Scholze; Georg Ellguth; Christian Mayr 001 (VLSI-SoC, 2019)

SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning. - Christian Mayr 001; Sebastian Höppner; Steve B. Furber (CoRR, 2019)

Efficient Reward-Based Structural Plasticity on a SpiNNaker 2 Prototype. - Yexin Yan; David Kappel; Felix Neumärker; Johannes Partzsch; Bernhard Vogginger; Sebastian Höppner; Steve B. Furber; Wolfgang Maass 001; Robert Legenstein; Christian Mayr 001 (IEEE Trans. Biomed. Circuits Syst., 2019)

Dynamic Power Management for Neuromorphic Many-Core Systems. - Sebastian Höppner; Bernhard Vogginger; Yexin Yan; Andreas Dixius; Stefan Scholze; Johannes Partzsch; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Georg Ellguth; Love Cederstroem; Luis A. Plana; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. - Dennis Walter; André Scharfe; Alexander Oefelein; Florian Schraut; Heiner Bauer; Farkas Csaszar; Robert Niebsch; Jörg Schreiter; Holger Eisenreich; Sebastian Höppner (COOL CHIPS, 2020)

Low-Power Low-Latency Keyword Spotting and Adaptive Control with a SpiNNaker 2 Prototype and Comparison with Loihi. - Yexin Yan; Terrence C. Stewart; Xuan Choo; Bernhard Vogginger; Johannes Partzsch; Sebastian Höppner; Florian Kelber; Chris Eliasmith; Steve B. Furber; Christian Mayr 001 (CoRR, 2020)

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology. - Sebastian Höppner; Holger Eisenreich; Dennis Walter; André Scharfe; Alexander Oefelein; Florian Schraut; Jörg Schreiter; Thorsten Riedel; Heiner Bauer; Robert Niebsch; Stephan Scherzer; Thomas Hocker; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System. - Johannes Partzsch; Christian Mayr 001; Massimiliano Giulioni; Marko Noack; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Paolo Del Giudice; René Schüffny (J. Signal Process. Syst., 2020)

Opportunities For A Hardware-Based OPC UA Server Implementation In Industry 4.0. - Zohra Charania; Chris Paul Iatrou; Valentin Khaydarov; Richard Jacob; Robert Wittig; Heiner Bauer; Sebastian Höppner; René Bachmann; Philipp Bauer; Hendrik Deckert; Christian Mayr 001; Gerhard P. Fettweis; et al. (IECON, 2021)

Ultra-High Compression of Twiddle Factor ROMs in Multi-Core DSP for FMCW Radars. - Hector A. Gonzalez; Florian Kelber; Marco Stolba; Chen Liu 031; Bernhard Vogginger; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Christian Mayr 001 (ISCAS, 2021)

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing. - Sebastian Höppner; Yexin Yan; Andreas Dixius; Stefan Scholze; Johannes Partzsch; Marco Stolba; Florian Kelber; Bernhard Vogginger; Felix Neumärker; Georg Ellguth; Stephan Hartmann 002; Stefan Schiefer; et al. (CoRR, 2021)

Comparing Loihi with a SpiNNaker 2 prototype on low-latency keyword spotting and adaptive robotic control. - Yexin Yan; Terrence C. Stewart; Xuan Choo; Bernhard Vogginger; Johannes Partzsch; Sebastian Höppner; Florian Kelber; Chris Eliasmith; Steve B. Furber; Christian Mayr 001 (Neuromorph. Comput. Eng., 2021)

Hardware Acceleration of EEG-Based Emotion Classification Systems: A Comprehensive Survey. - Hector A. Gonzalez; Richard George 001; Shahzad Muzaffar; Javier Acevedo; Sebastian Höppner; Christian Mayr 001; Jerald Yoo; Frank H. P. Fitzek; Ibrahim M. Elfadel (IEEE Trans. Biomed. Circuits Syst., 2021)

Hardware Implementation of an OPC UA Server for Industrial Field Devices. - Heiner Bauer; Sebastian Höppner; Chris Paul Iatrou; Zohra Charania; Stephan Hartmann 002; Saif-Ur Rehman; Andreas Dixius; Georg Ellguth; Dennis Walter; Johannes Uhlig; Felix Neumärker; Marc Berthel; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2021)

ZEN: A flexible energy-efficient hardware classifier exploiting temporal sparsity in ECG data. - Matthias Jobst; Johannes Partzsch; Chen Liu 031; Liyuan Guo; Dennis Walter; Saif-Ur Rehman; Stefan Scholze; Sebastian Höppner; Christian Mayr 001 (AICAS, 2022)

A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI. - Mattis Hasler; Sebastian Haas; Robert Wittig; Stefan Scholze; Andreas Dixius; Sebastian Höppner; Gerhard P. Fettweis; Christian Mayr 001 (ISVLSI, 2022)

A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm. - Franz Marcus Schüffny; Stefan Hänzsche; Marc Berthel; Seyed Mohammad Ali Zeinolabedin; Stefan Scholze; Sebastian Höppner; Richard Miru George; Christian Mayr 001 (NorCAS, 2022)

How to design an input stage for neural recording system in 22 nm FDSOI. - Franz Marcus Schüffny; Sebastian Höppner; Seyed Mohammad Ali Zeinolabedin; Richard Miru George; Christian Mayr 001 (PRIME, 2022)

A 16-Channel Fully Configurable Neural SoC With 1.52 $ mu$W/Ch Signal Acquisition, 2.79 $ mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI. - Seyed Mohammad Ali Zeinolabedin; Franz Marcus Schüffny; Richard George 001; Florian Kelber; Heiner Bauer; Stefan Scholze; Stefan Hänzsche; Marco Stolba; Andreas Dixius; Georg Ellguth; Dennis Walter; Sebastian Höppner; et al. (IEEE Trans. Biomed. Circuits Syst., 2022)

An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology. - Franz Marcus Schüffny; Sebastian Höppner; Stefan Hänzsche; Richard Miru George; Seyed Mohammad Ali Zeinolabedin; Christian Mayr 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power. - Hector A. Gonzalez; Bernhard Vogginger; Chen Liu 031; Marco Stolba; Florian Kelber; Heiner Bauer; Stefan Hänzsche; Stefan Scholze; Marc Berthel; Tim Rosmeisl; Liyuan Guo; Dennis Walter; et al. (CICC, 2023)

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. - Heiner Bauer; Marco Stolba; Stefan Scholze; Dennis Walter; Christian Mayr 001; Alexander Oefelein; Sebastian Höppner; André Scharfe; Florian Schraut; Holger Eisenreich (ISOCC, 2023)

A 3.3V Saturation-Aware Neurostimulator with Reset Functionality in 22 nm FDSOI. - Franz Marcus Schüffny; Stefan Hänzsche; Stephan Henker; Seyed Mohammad Ali Zeinolabedin; Stefan Scholze; Sebastian Höppner; Richard Miru George; Christian Mayr 001 (NEWCAS, 2023)