VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. - Sebastian Huhn 001; Stephan Eggersglüß; Rolf Drechsler (ETS, 2016)

Exploring superior structural materials using multi-objective optimization and formal techniques. - Rolf Drechsler; Stephan Eggersglüß; Nils Ellendt; Sebastian Huhn 001; Lutz Mädler (ISED, 2016)

Enhancing robustness of sequential circuits using application-specific knowledge and formal methods. - Sebastian Huhn 001; Stefan Frehse; Robert Wille; Rolf Drechsler (ASP-DAC, 2017)

Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. - Sebastian Huhn 001; Stephan Eggersglüß; Krishnendu Chakrabarty; Rolf Drechsler (DATE, 2017)

Reconfigurable TAP controllers with embedded compression for large test data volume. - Sebastian Huhn 001; Stephan Eggersglüß; Rolf Drechsler (DFT, 2017)

Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements. - Sebastian Huhn 001; Heike Sonnenberg; Stephan Eggersglüß; Brigitte Clausen; Rolf Drechsler (SSCI, 2017)

SAT-Lancer: A Hardware SAT-Solver for Self-Verification. - Buse Ustaoglu; Sebastian Huhn 001; Daniel Große; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2018)

Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems. - Jannis Stoppe; Christina Plump; Sebastian Huhn 001; Rolf Drechsler (LDIC, 2018)

SAT-Hard: A Learning-Based Hardware SAT-Solver. - Buse Ustaoglu; Sebastian Huhn 001; Frank Sill Torres; Daniel Große; Rolf Drechsler (DSD, 2019)

Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns. - Sebastian Huhn 001; Daniel Tille; Rolf Drechsler (ETS, 2019)

A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems. - Sebastian Huhn 001; Daniel Tille; Rolf Drechsler (ITC-Asia, 2019)

Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits. - Sebastian Huhn 001; Stefan Frehse; Robert Wille; Rolf Drechsler (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains. - Payam Habiby; Sebastian Huhn 001; Rolf Drechsler (DFT, 2020)

Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials. - Rolf Drechsler; Sebastian Huhn 001; Christina Plump (DSD, 2020)

Next generation design for testability, debug and reliability using formal techniques. - Sebastian Huhn 001 (2020)

A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks. - Marcel Merten; Sebastian Huhn 001; Rolf Drechsler (DFT, 2021)

Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability. - Payam Habiby; Sebastian Huhn 001; Rolf Drechsler (DTIS, 2021)

Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods. - Marcel Merten; Sebastian Huhn 001; Rolf Drechsler (ETS, 2022)

Next Generation Design For Testability, Debug and Reliability Using Formal Techniques. - Sebastian Huhn 001; Rolf Drechsler (ITC, 2022)

A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection. - Marcel Merten; Sebastian Huhn 001; Rolf Drechsler (VTS, 2022)

Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors. - Jens Trommer; Niladri Bhattacharjee; Thomas Mikolajick; Sebastian Huhn 001; Marcel Merten; Mohammed E. Djeridane; Muhammad Hassan 002; Rolf Drechsler; Shubham Rai; Nima Kavand; Armin Darjani; Akash Kumar 001; et al. (DATE, 2023)

RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks. - Payam Habiby; Sebastian Huhn 001; Rolf Drechsler (DFT, 2023)

Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. - Payam Habiby; Natalia Lylina; Chih-Hao Wang; Hans-Joachim Wunderlich; Sebastian Huhn 001; Rolf Drechsler (ETS, 2023)

Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods. - Marcel Merten; Sebastian Huhn 001; Rolf Drechsler (ETS, 2023)

A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin. - Daniel Tille; Leon Klimasch; Sebastian Huhn 001 (VTS, 2023)

A Multi-Objective Evolutionary Approach for Test Network Design. - Payam Habiby; Fatemeh Shirinzadeh; Sebastian Huhn 001; Rolf Drechsler (ETS, 2024)

Self-Aware Silicon: Enhancing Lifecycle Management with Intelligent Testing and Data Insights. - Fabian Vargas 001; Marko S. Andjelkovic; Milos Krstic; Anirban Kar; Swati Deshwal; Yogesh S. Chauhan; Hussam Amrouch; Daniel Tille; Sebastian Huhn 001 (ETS, 2025)