Parallel Macro Pipelining on the Intel SCC Many-Core Computer. - Tim Süß; Andrew Schoenrock; Sebastian Meisner; Christian Plessl (IPDPS Workshops, 2013)

Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. - Jahanzeb Anwer; Sebastian Meisner; Marco Platzner (ReConFig, 2013)

Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. - Sebastian Meisner; Marco Platzner (ARC, 2014)

FPGA Redundancy Configurations: An Automated Design Space Exploration. - Jahanzeb Anwer; Marco Platzner; Sebastian Meisner (IPDPS Workshops, 2014)

Comparison of thread signatures for error detection in hybrid multi-cores. - Sebastian Meisner; Marco Platzner (FPT, 2015)

Thread shadowing: On the effectiveness of error detection at the hardware thread level. - Sebastian Meisner; Marco Platzner (ReConFig, 2016)

Dynamic Reliability Management for FPGA-Based Systems. - Jahanzeb Anwer; Sebastian Meisner; Marco Platzner (Int. J. Reconfigurable Comput., 2020)