Combining instruction set simulation and WCET analysis for embedded software performance estimation. - Stefan Stattelmann; Sebastian Ottlik; Alexander Viehl; Oliver Bringmann 001; Wolfgang Rosenstiel (SIES, 2012)

Context-sensitive timing simulation of binary embedded software. - Sebastian Ottlik; Stefan Stattelmann; Alexander Viehl; Wolfgang Rosenstiel; Oliver Bringmann 001 (CASES, 2014)

Trace-based context-sensitive timing simulation considering execution path variations. - Sebastian Ottlik; Jan Micha Borrmann; Sadik Asbach; Alexander Viehl; Wolfgang Rosenstiel; Oliver Bringmann 001 (ASP-DAC, 2016)

Context-sensitive timing automata for fast source level simulation. - Sebastian Ottlik; Christoph Gerum; Alexander Viehl; Wolfgang Rosenstiel; Oliver Bringmann 001 (DATE, 2017)

Timing Models for Fast Embedded Software Performance Analysis. - Oliver Bringmann 001; Christoph Gerum; Sebastian Ottlik (Handbook of Hardware/Software Codesign, 2017)

Precise Software Timing Simulation Considering Execution Contexts. - Oliver Bringmann 001; Sebastian Ottlik; Alexander Viehl (Handbook of Hardware/Software Codesign, 2017)