Optimized Data-Reuse in Processor Arrays. - Sebastian Siegel; Renate Merker (ASAP, 2004)

A Parallel Hardware-Software System for Signal Processing Algorithms. - Mathias Kortke; Jan Müller 001; Rainer Schaffer; Sebastian Siegel; Renate Merker; Jürgen Kelber (PARELEC, 2004)

Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays. - Sebastian Siegel; Renate Merker (PARELEC, 2004)

Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching. - Markus Rullmann; Sebastian Siegel; Renate Merker (IPDPS, 2005)

Co-Design of Massively Parallel Embedded Processor Architectures. - Frank Hannig; Hritam Dutta; Alexey Kupriyanov; Jürgen Teich; Rainer Schaffer; Sebastian Siegel; Renate Merker; Ronan Keryell; Bernard Pottier; Daniel Chillet; Daniel Ménard; Olivier Sentieys (ReCoSoC, 2005)

Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy. - Sebastian Siegel; Renate Merker (ASAP, 2006)

Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints. - Sebastian Siegel; Renate Merker (Euro-Par, 2006)

Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels. - Sebastian Siegel; Rainer Schaffer; Renate Merker (PARELEC, 2006)

Massively Parallel Processor Architectures: A Co-design Approach. - Hritam Dutta; Frank Hannig; Alexey Kupriyanov; Dmitrij Kissler; Jürgen Teich; Rainer Schaffer; Sebastian Siegel; Renate Merker; Bernard Pottier (ReCoSoC, 2007)

Abbildungsverfahren zur effizienten Implementierung rechenintensiver Algorithmen auf Prozessorarrays. - Sebastian Siegel (2007)

Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. - Felix Staudigl; Mohammed Hossein; Tobias Ziegler 005; Hazem Al Indari; Rebecca Pelke; Sebastian Siegel; Dirk J. Wouters; Dominik Sisejkovic; Jan Moritz Joseph; Rainer Leupers (CODES+ISSS, 2023)

Demonstration of neuromorphic sequence learning on a memristive array. - Sebastian Siegel; Tobias Ziegler 005; Younes Bouhadjar; Tom Tetzlaff; Rainer Waser; Regina Dittmann; Dirk J. Wouters (NICE, 2023)

System model of neuromorphic sequence learning on a memristive crossbar array. - Sebastian Siegel; Younes Bouhadjar; Tom Tetzlaff; Rainer Waser; Regina Dittmann; Dirk J. Wouters (Neuromorph. Comput. Eng., 2023)

Sequence learning in a spiking neuronal network with memristive synapses. - Younes Bouhadjar; Sebastian Siegel; Tom Tetzlaff; Markus Diesmann; Rainer Waser; Dirk J. Wouters (Neuromorph. Comput. Eng., 2023)

The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming. - Zhenming Yu; Ming-Jay Yang; Jan Finkbeiner; Sebastian Siegel; John Paul Strachan; Emre Neftci (AICAS, 2024)

Synaptogen: A cross-domain generative device model for large-scale neuromorphic circuit design. - Tyler Hennen; Leon Brackmann; Tobias Ziegler 005; Sebastian Siegel; Stephan Menzel; Rainer Waser; Dirk J. Wouters; Daniel Bedau (CoRR, 2024)

Analog In-Memory Computing Attention Mechanism for Fast and Energy-Efficient Large Language Models. - Nathan Leroux; Paul-Philipp Manea; Chirag Sudarshan; Jan Finkbeiner; Sebastian Siegel; John Paul Strachan; Emre Neftci (CoRR, 2024)

IMSSA: Deploying modern state-space models on memristive in-memory compute hardware. - Sebastian Siegel; Ming-Jay Yang; John Paul Strachan (ISCAS, 2025)

Real-time raw signal genomic analysis using fully integrated memristor hardware. - Peiyi He; Shengbo Wang; Ruibin Mao; Sebastian Siegel; Giacomo Pedretti; Jim Ignowski; John Paul Strachan; Ruibang Luo; Can Li (CoRR, 2025)

QS4D: Quantization-aware training for efficient hardware deployment of structured state-space sequential models. - Sebastian Siegel; Ming-Jay Yang; Younes Bouhadjar; Maxime Fabre; Emre Neftci; John Paul Strachan (CoRR, 2025)