Formale Verifikation der Architekturverbesserung eines Viterbi Decoder IP Blocks. - Matthias Mutz; Sebastian Steibl (MBMV, 1999)

Intel® atomTM processor core made FPGA-synthesizable. - Perry H. Wang; Jamison D. Collins; Christopher T. Weaver; Belliappa Kuttanna; Shahram Salamian; Gautham N. Chinya; Ethan Schuchman; Oliver Schilling; Thorsten Doil; Sebastian Steibl; Hong Wang 003 (FPGA, 2009)

Intel nehalem processor core made FPGA synthesizable. - Graham Schelle; Jamison D. Collins; Ethan Schuchman; Perry H. Wang; Xiang Zou; Gautham N. Chinya; Ralf Plate; Thorsten Mattner; Franz Olbrich; Per Hammarlund; Ronak Singhal; Jim Brayton; et al. (FPGA, 2010)

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. - Jason Howard; Saurabh Dighe; Yatin Vasant Hoskote; Sriram R. Vangal; David Finan; Gregory Ruhl; David Jenkins; Howard Wilson; Nitin Borkar; Gerhard Schrom; Fabric Pailet; Shailendra Jain; et al. (ISSCC, 2010)

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. - Jason Howard; Saurabh Dighe; Sriram R. Vangal; Gregory Ruhl; Nitin Borkar; Shailendra Jain; Vasantha Erraguntla; Michael Konow; Michael Riepen; Matthias Gries; Guido Droege; Tor Lund-Larsen; et al. (IEEE J. Solid State Circuits, 2011)