Coherency Hub Design for Multi-Node Victoria Falls Server Systems. - John R. Feehrer; Paul Rotker; Milton Shih; Paul Gingras; Peter Yakutis; Stephen Phillips; John Heath; Sebastian Turullols (Hot Interconnects, 2008)

SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-sockets. - Sebastian Turullols; Ram Sivaramakrishnan (Hot Chips Symposium, 2012)

The next-generation 64b SPARC core in a T4 SoC processor. - Jinuk Luke Shin; Heechoul Park; Hongping Penny Li; Alan P. Smith 002; Youngmoon Choi; Harikaran Sathianathan; Sudesna Dash; Sebastian Turullols; Song Kim; Robert P. Masleid; Georgios K. Konstadinidis; Robert T. Golla; et al. (ISSCC, 2012)

3.6GHz 16-core SPARC SoC processor in 28nm. - Jason Hart; Steve Butler; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Lance Kwong; Robert P. Masleid; et al. (ISSCC, 2013)

Bandwidth and power management of glueless 8-socket SPARC T5 system. - Venkatram Krishnaswamy; Dawei Huang; Sebastian Turullols; Jinuk Luke Shin (ISSCC, 2013)

The Next Generation 64b SPARC Core in a T4 SoC Processor. - Jinuk Luke Shin; Robert T. Golla; Hongping Penny Li; Sudesna Dash; Youngmoon Choi; Alan P. Smith 002; Harikaran Sathianathan; Mayur Joshi; Heechoul Park; Mohamed Elgebaly; Sebastian Turullols; Song Kim; et al. (IEEE J. Solid State Circuits, 2013)

The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets. - John R. Feehrer; Sumti Jairath; Paul Loewenstein; Ram Sivaramakrishnan; David Smentek; Sebastian Turullols; Ali Vahidsafa (IEEE Micro, 2013)

Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor. - Yifan YangGong; Sebastian Turullols; Daniel Woo; Changku Huang; King C. Yen; Venkatram Krishnaswamy; Kalon Holdbrook; Jinuk Luke Shin (A-SSCC, 2014)

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm. - Jason Hart; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Venkatram Krishnaswamy; Lance Kwong; Robert P. Masleid; et al. (IEEE J. Solid State Circuits, 2014)

4.3 Fine-grained adaptive power management of the SPARC M7 processor. - Venkatram Krishnaswamy; Jeffrey Brooks; Georgios K. Konstadinidis; Curtis McAllister; Ha Pham; Sebastian Turullols; Jinuk Luke Shin; Yifan YangGong; Haowei Zhang (ISSCC, 2015)

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. - Georgios K. Konstadinidis; Hongping Penny Li; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; Vijay Srinivasan; et al. (IEEE J. Solid State Circuits, 2016)