Area time power estimation for FPGA based designs at a behavioral level. - Sébastien Bilavarn; Guy Gogniat; Jean Luc Philippe (ICECS, 2000)

Exploration Architecturale au Niveau Comportemental - Application aux FPGAs. (Architectural Exploration in behavioral level - Application to FPGAs). - Sébastien Bilavarn (2002)

An estimation and exploration methodology from system-level specifications: application to FPGAs. - Sébastien Bilavarn; Guy Gogniat; Jean Luc Philippe (FPGA, 2003)

Fast prototyping of reconfigurable architectures from a C program. - Sébastien Bilavarn; Guy Gogniat; Jean Luc Philippe; Lilian Bossuet (ISCAS (5), 2003)

Reconfigurable coprocessor for media streaming. - Sébastien Bilavarn; Eric Debes (ICME, 2004)

Processor Enhancements for Media Streaming Applications. - Sébastien Bilavarn; Eric Debes; Pierre Vandergheynst; Jean-Philippe Diguet (J. VLSI Signal Process., 2005)

EPICURE: A partitioning and co-design framework for reconfigurable computing. - Jean-Philippe Diguet; Guy Gogniat; Jean Luc Philippe; Yannick Le Moullec; Sébastien Bilavarn; Christian Gamrat; Karim Ben Chehida; Michel Auguin; Xavier Fornari; Philippe Kajfasz (Microprocess. Microsystems, 2006)

Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations. - Sébastien Bilavarn; Guy Gogniat; Jean Luc Philippe; Lilian Bossuet (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations. - Sébastien Bilavarn; Cécile Belleudy; Michel Auguin; T. Dupont; Anne-Marie Fouilliart (DSD, 2008)

UML profile for estimating application Worst Case Execution Time on System-on-Chip. - Fateh Boutekkouk; Sébastien Bilavarn; Michel Auguin; Mohammed Benmohammed (SoC, 2008)

UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs). - Fateh Boutekkouk; Mohamed Benmohammed; Sébastien Bilavarn; Michel Auguin (J. Object Technol., 2009)

UML for Modelling and Performance Estimation of Embedded Systems. - Fateh Boutekkouk; Mohamed Benmohammed; Sébastien Bilavarn; Michel Auguin (J. Object Technol., 2009)

Power Consumption Modeling for DVFS Exploitation. - Andrea Castagnetti; Cécile Belleudy; Sébastien Bilavarn; Michel Auguin (DSD, 2010)

Implantation d'un décodeur H.264 sur plateforme multiprocesseur avec gestion énergétique. - Sébastien Bilavarn; Cécile Belleudy; Michel Auguin; T. Dupont; Anna-Marie Fouillart (Tech. Sci. Informatiques, 2010)

A Video Monitoring Application forWireless Sensor Networks using IEEE 802.15.4. - Sébastien Bilavarn; Andrea Castagnetti; Laurent Rodriguez (ARCS Workshops, 2011)

Embedded operating systems energy overhead. - Bassem Ouni; Cécile Belleudy; Sébastien Bilavarn; Eric Senn (DASIP, 2011)

Towards a power and energy efficient use of partial dynamic reconfiguration. - Robin Bonamy; Daniel Chillet; Olivier Sentieys; Sébastien Bilavarn (ReCoSoC, 2011)

Exploitation of the EDF Scheduling in the Wireless Sensors Networks. - Rym Chéour; Sébastien Bilavarn; Mohamed Abid (Int. J. Meas. Technol. Instrum. Eng., 2011)

AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC. - Dominique Blouin; Daniel Chillet; Eric Senn; Sébastien Bilavarn; Robin Bonamy; Christian Samoyeau (Int. J. Reconfigurable Comput., 2011)

Parallelism Level Impact on Energy Consumption in Reconfigurable Devices. - Robin Bonamy; Daniel Chillet; Olivier Sentieys; Sébastien Bilavarn (SIGARCH Comput. Archit. News, 2011)

Open-People: Open Power and Energy Optimization PLatform and Estimator. - Eric Senn; Daniel Chillet; Olivier Zendra; Cécile Belleudy; Sébastien Bilavarn; Rabie Ben Atitallah; Christian Samoyeau; A. Fritsch (DSD, 2012)

Impact of operating points on DVFS power management. - Jabran Khan; Sébastien Bilavarn; Cécile Belleudy (DTIS, 2012)

Power consumption model for partial and dynamic reconfiguration. - Robin Bonamy; Daniel Chillet; Sébastien Bilavarn; Olivier Sentieys (ReConFig, 2012)

Energy Analysis of a Real-time Multiprocessor Control of Idle States. - Jabran Khan; Sébastien Bilavarn; Muhammad Khurram Bhatti; Cécile Belleudy (PECCS, 2013)

Power consumption models for the use of dynamic and partial reconfiguration. - Robin Bonamy; Sébastien Bilavarn; Daniel Chillet; Olivier Sentieys (Microprocess. Microsystems, 2014)

HLS based design of a mixed architecture for H.264/AVC CAVLD. - Taheni Damak; Sébastien Bilavarn; Nouri Masmoudi (SSD, 2015)

An energy-aware scheduler for dynamically reconfigurable multi-core systems. - Robin Bonamy; Sébastien Bilavarn; Fabrice Muller (ReCoSoC, 2015)

FoRTReSS: a flow for design space exploration of partially reconfigurable systems. - François Duhem; Fabrice Muller; Robin Bonamy; Sébastien Bilavarn (Des. Autom. Embed. Syst., 2015)

Efficiency Modeling and Analysis of 64-bit ARM Clusters for HPC. - Joël Wanza Weloli; Sébastien Bilavarn; Said Derradji; Cécile Belleudy; Sylvie Lesmanne (DSD, 2016)

Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems. - Robin Bonamy; Sébastien Bilavarn; Daniel Chillet; Olivier Sentieys (J. Low Power Electron., 2016)

Effectiveness of power strategies for video applications: a practical study. - Sébastien Bilavarn; Jabran Khan; Cécile Belleudy; Muhammad Khurram Bhatti (J. Real Time Image Process., 2016)

Efficiency modeling and exploration of 64-bit ARM compute nodes for exascale. - Joël Wanza Weloli; Sébastien Bilavarn; Maarten de Vries; Said Derradji; Cécile Belleudy (Microprocess. Microsystems, 2017)

Modélisation, Conception Système d'Architectures Hétérogènes pour les Applications Embarquées : Eléments d'amélioration de l'efficacité énergétique des systèmes sur puce de silicium. (Modelling, Design of Heterogenous architectures for embedded Applications / Modelling, Design of Heterogenous architectures for embedded Applications : Refinement parts about power efficiency of silicon chips systems). - Sébastien Bilavarn (2018)

Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart camera. - Robin Bonamy; Sébastien Bilavarn; Fabrice Muller; François Duhem; Simon Heywood; Philippe Millet; Fabrice Lemonnier (Int. J. Circuit Theory Appl., 2018)

An FPGA-Based Hybrid Neural Network Accelerator for Embedded Satellite Image Classification. - Edgar Lemaire; Matthieu Moretti; Lionel Daniel; Benoît Miramond; Philippe Millet; Frédéric Feresin; Sébastien Bilavarn (ISCAS, 2020)

Efficiency analysis of artificial vs. Spiking Neural Networks on FPGAs. - Zhuoer Li; Edgar Lemaire; Nassim Abderrahmane; Sébastien Bilavarn; Benoît Miramond (J. Syst. Archit., 2022)

Synaptic Activity and Hardware Footprint of Spiking Neural Networks in Digital Neuromorphic Systems. - Edgar Lemaire; Benoît Miramond; Sébastien Bilavarn; Hadi Saoud; Nassim Abderrahmane (ACM Trans. Embed. Comput. Syst., 2022)

Improving the Energy Efficiency of CNN Inference on FPGA Using Partial Reconfiguration. - Zhuoer Li; Sébastien Bilavarn (DASIP, 2024)

Partial Reconfiguration for Energy-Efficient Inference on FPGA: A Case Study with ResNet-18. - Zhuoer Li; Sébastien Bilavarn (DSD, 2024)

Control Enhancement of Traction Electric Drives Using Neural Network Predictive Controller. - Romain Cocogne; Sébastien Bilavarn; Mostafa El Mokadem; Khaled Douzane (ICCAD, 2024)