16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors. - Laurent Grenouillet; Niccolo Castellani; Alain Persico; Valentina Meli; Simon Martin 006; Olivier Billoint; R. Segaud; Stefania Bernasconi; C. Pellissier; Carine Jahan; Christelle Charpin-Nicolle; P. Dezest; et al. (IMW, 2021)

Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro. - Bastien Giraud; Sebastien Ricavy; Yasser Moursy; Cyrille Laffond; Ilan Sever; Valentin Gherman; Manuel Pezzin; Florent Lepin; Mariam Diallo; Khadija Zenati; Sylvain Dumas; Maxim Vershkov; et al. (IMW, 2023)

A synergistic fault tolerance framework for Mbit 28nm embedded RRAM. - Papavramidou Panagiota; Sebastien Ricavy; Christopher Mounet; Carine Jahan; Niccolo Castellani; François Andrieu (IOLTS, 2024)

Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro. - Bastien Giraud; Sebastien Ricavy; Cyrille Laffond; Ilan Sever; Valentin Gherman; Florent Lepin; Mariam Diallo; Khadija Zenati; Sylvain Dumas; Olivier Guille; Maxim Vershkov; Alessandro Bricalli; et al. (IEEE J. Solid State Circuits, 2024)