A C to Hardware/Software Compiler. - Kia Bazargan; Ryan Kastner; Seda Ogrenci; Majid Sarrafzadeh (FCCM, 2000)

RPack: routability-driven packing for cluster-based FPGAs. - Elaheh Bozorgzadeh; Seda Ogrenci Memik; Majid Sarrafzadeh (ASP-DAC, 2001)

Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. - Kia Bazargan; Seda Ogrenci; Majid Sarrafzadeh (DAC, 2001)

Instruction Generation for Hybrid Reconfigurable Systems. - Ryan Kastner; Seda Ogrenci Memik; Elaheh Bozorgzadeh; Majid Sarrafzadeh (ICCAD, 2001)

A Super-Scheduler for Embedded Reconfigurable Systems. - Seda Ogrenci Memik; Elaheh Bozorgzadeh; Ryan Kastner; Majid Sarrafzadeh (ICCAD, 2001)

Fast floorplanning for effective prediction and construction. - Abhishek Ranjan; Kia Bazargan; Seda Ogrenci; Majid Sarrafzadeh (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic. - Gokhan Memik; Seda Ogrenci Memik; William H. Mangione-Smith (FCCM, 2002)

Accelerated SAT-based Scheduling of Control/Data Flow Graphs. - Seda Ogrenci Memik; Farzan Fallah (ICCD, 2002)

Early evaluation techniques for low power binding. - Eren Kursun; Ankur Srivastava 001; Seda Ogrenci Memik; Majid Sarrafzadeh (ISLPED, 2002)

Instruction generation for hybrid reconfigurable systems. - Ryan Kastner; Adam Kaplan; Seda Ogrenci Memik; Elaheh Bozorgzadeh (ACM Trans. Design Autom. Electr. Syst., 2002)

Global resource sharing for synthesis of control data flow graphs on FPGAs. - Seda Ogrenci Memik; Gokhan Memik; Roozbeh Jafari; Eren Kursun (DAC, 2003)

Achieving Design Closure Through Delay Relaxation Parameter. - Ankur Srivastava 001; Seda Ogrenci Memik; Bo-Kyung Choi; Majid Sarrafzadeh (ICCAD, 2003)

Analysis and FPGA Implementation of Image Restoration under Resource Constraints. - Seda Ogrenci Memik; Aggelos K. Katsaggelos; Majid Sarrafzadeh (IEEE Trans. Computers, 2003)

Power Management for FPGAs: Power-Driven Design Partitioning. - Rajarshi Mukherjee; Seda Ogrenci Memik (FCCM, 2004)

Power-Driven Design Partitioning. - Rajarshi Mukherjee; Seda Ogrenci Memik (FPL, 2004)

Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs. - Elaheh Bozorgzadeh; Seda Ogrenci Memik; Xiaojian Yang; Majid Sarrafzadeh (J. Circuits Syst. Comput., 2004)

Resource sharing in pipelined CDFG synthesis. - Somsubhra Mondal; Seda Ogrenci Memik (ASP-DAC, 2005)

Evaluation of dual VDD fabrics for low power FPGAs. - Rajarshi Mukherjee; Seda Ogrenci Memik (ASP-DAC, 2005)

Temperature-aware resource allocation and binding in high-level synthesis. - Rajarshi Mukherjee; Seda Ogrenci Memik; Gokhan Memik (DAC, 2005)

Hierarchical LUT structures for leakage power reduction (abstract only). - Somsubhra Mondal; Seda Ogrenci Memik; Debasish Das (FPGA, 2005)

Real-Time Feature Extraction for High Speed Networks. - David Nguyen; Gokhan Memik; Seda Ogrenci Memik; Alok N. Choudhary (FPL, 2005)

Fine-grain leakage optimization in SRAM based FPGAs. - Somsubhra Mondal; Seda Ogrenci Memik (ACM Great Lakes Symposium on VLSI, 2005)

Quick Reconfiguration in Clustered Micro-Sequencer. - Roozbeh Jafari; Seda Ogrenci Memik; Majid Sarrafzadeh (IPDPS, 2005)

A low power FPGA routing architecture. - Somsubhra Mondal; Seda Ogrenci Memik (ISCAS (2), 2005)

Peak temperature control and leakage reduction during binding in high level synthesis. - Rajarshi Mukherjee; Seda Ogrenci Memik; Gokhan Memik (ISLPED, 2005)

Early Quality Assessment for Low Power Behavioral Synthesis. - Eren Kursun; Rajarshi Mukherjee; Seda Ogrenci Memik (J. Low Power Electron., 2005)

On effective slack management in postscheduling phase. - Ankur Srivastava 001; Seda Ogrenci Memik; Bo-Kyung Choi; Majid Sarrafzadeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A scheduling algorithm for optimization and early planning in high-level synthesis. - Seda Ogrenci Memik; Ryan Kastner; Elaheh Bozorgzadeh; Majid Sarrafzadeh (ACM Trans. Design Autom. Electr. Syst., 2005)

Systematic temperature sensor allocation and placement for microprocessors. - Rajarshi Mukherjee; Seda Ogrenci Memik (DAC, 2006)

A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead. - Rajarshi Mukherjee; Somsubhra Mondal; Seda Ogrenci Memik (ERSA, 2006)

Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs. - Somsubhra Mondal; Seda Ogrenci Memik; Nikolaos Bellas (FCCM, 2006)

Adaptive Metrics for System-Level Functional Partitioning. - Giovanni Agosta; Marco D. Santambrogio; Seda Ogrenci Memik (FDL, 2006)

Power Optimization Techniques for SRAM-Based FPGAs. - Somsubhra Mondal; Seda Ogrenci Memik (FPL, 2006)

Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators. - Somsubhra Mondal; Seda Ogrenci Memik; Nikolaos Bellas (FPL, 2006)

Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology. - Vincenzo Rana; Marco D. Santambrogio; Seda Ogrenci Memik; Donatella Sciuto (FPT, 2006)

Physical aware frequency selection for dynamic thermal management in multi-core systems. - Rajarshi Mukherjee; Seda Ogrenci Memik (ICCAD, 2006)

Thermal sensor allocation and placement for reconfigurable systems. - Rajarshi Mukherjee; Somsubhra Mondal; Seda Ogrenci Memik (ICCAD, 2006)

Thermal-induced leakage power optimization by redundant resource allocation. - Min Ni; Seda Ogrenci Memik (ICCAD, 2006)

Fine-grain thermal profiling and sensor insertion for FPGAs. - Somsubhra Mondal; Rajarshi Mukherjee; Seda Ogrenci Memik (ISCAS, 2006)

An Integrated Approach to Thermal Management in High-Level Synthesis. - Rajarshi Mukherjee; Seda Ogrenci Memik (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Self-heating-aware optimal wire sizing under Elmore delay model. - Min Ni; Seda Ogrenci Memik (DATE, 2007)

A self-adjusting clock tree architecture to cope with temperature variations. - Jieyi Long; Ja Chun Ku; Seda Ogrenci Memik; Yehea I. Ismail (ICCAD, 2007)

Early planning for clock skew scheduling during register binding. - Min Ni; Seda Ogrenci Memik (ICCAD, 2007)

A novel SoC design methodology combining adaptive software and reconfigurable hardware. - Marco D. Santambrogio; Seda Ogrenci Memik; Vincenzo Rana; Umut A. Acar; Donatella Sciuto (ICCAD, 2007)

Managing Reconfigurable Resources in Heterogeneous Cores Using Portable Pre-Synthesized Templates. - Marco D. Santambrogio; Matteo Giani; Seda Ogrenci Memik (SoC, 2007)

A power and temperature aware DRAM architecture. - Song Liu; Seda Ogrenci Memik; Yu Zhang; Gokhan Memik (DAC, 2008)

Automated design of self-adjusting pipelines. - Jieyi Long; Seda Ogrenci Memik (DAC, 2008)

Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction. - Min Ni; Seda Ogrenci Memik (DAC, 2008)

Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system. - Brian Leung; Yan Pan 010; Christopher L. Schroeder; Seda Ogrenci Memik; Gokhan Memik; Mitra J. Z. Hartmann (FPL, 2008)

An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction. - Jieyi Long; Hai Zhou 001; Seda Ogrenci Memik (ISPD, 2008)

A Reconfiguration-Aware Floorplacer for FPGAs. - Alessio Montone; Francesco Redaelli; Marco D. Santambrogio; Seda Ogrenci Memik (ReConFig, 2008)

Thermal monitoring mechanisms for chip multiprocessors. - Jieyi Long; Seda Ogrenci Memik; Gokhan Memik; Rajarshi Mukherjee (ACM Trans. Archit. Code Optim., 2008)

EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm. - Jieyi Long; Hai Zhou 001; Seda Ogrenci Memik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Presynthesis Area Estimation of Reconfigurable Streaming Accelerators. - Seda Ogrenci Memik; Nikolaos Bellas; Somsubhra Mondal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Optimizing Thermal Sensor Allocation for Microprocessors. - Seda Ogrenci Memik; Rajarshi Mukherjee; Min Ni; Jieyi Long (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A high-level clustering algorithm targeting dual Vdd FPGAs. - Rajarshi Mukherjee; Song Liu; Seda Ogrenci Memik; Somsubhra Mondal (ACM Trans. Design Autom. Electr. Syst., 2008)

FPGA Implementation of the Interior-Point Algorithm with Applications to Collision Detection. - Chih-Hung Wu; Seda Ogrenci Memik; Sanjay Mehrotra (FCCM, 2009)

An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures. - Francesco Redaelli; Marco D. Santambrogio; Seda Ogrenci Memik (Int. J. Reconfigurable Comput., 2009)

A framework for optimizing thermoelectric active cooling systems. - Jieyi Long; Seda Ogrenci Memik (DAC, 2010)

Using Speculative Functional Units in high level synthesis. - Alberto A. Del Barrio; María C. Molina; Jose Manuel Mendias; Román Hermida; Seda Ogrenci Memik (DATE, 2010)

Optimization of the bias current network for accurate on-chip thermal monitoring. - Jieyi Long; Seda Ogrenci Memik (DATE, 2010)

Inversed Temperature Dependence aware clock skew scheduling for sequential circuits. - Jieyi Long; Seda Ogrenci Memik (DATE, 2010)

Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers. - Jieyi Long; Seda Ogrenci Memik; Matthew Grayson (DATE, 2010)

An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs. - Brian Leung; Chih-Hung Wu; Seda Ogrenci Memik; Sanjay Mehrotra (FPL, 2010)

A revisit to the primal-dual based clock skew scheduling algorithm. - Min Ni; Seda Ogrenci Memik (ISQED, 2010)

Placement and Floorplanning in Dynamically Reconfigurable FPGAs. - Alessio Montone; Marco D. Santambrogio; Donatella Sciuto; Seda Ogrenci Memik (ACM Trans. Reconfigurable Technol. Syst., 2010)

An Approach for Adaptive DRAM Temperature and Power Management. - Song Liu; Yu Zhang; Seda Ogrenci Memik; Gokhan Memik (IEEE Trans. Very Large Scale Integr. Syst., 2010)

SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation. - Jieyi Long; Ja Chun Ku; Seda Ogrenci Memik; Yehea I. Ismail (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A Fast Heuristic Algorithm for Multidomain Clock Skew Scheduling. - Min Ni; Seda Ogrenci Memik (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Power optimization in heterogenous datapaths. - Alberto A. Del Barrio; Seda Ogrenci Memik; María C. Molina; José M. Mendías; Román Hermida (DATE, 2011)

Hardware/software techniques for DRAM thermal management. - Song Liu; Brian Leung; Alexander Neckar; Seda Ogrenci Memik; Gokhan Memik; Nikos Hardavellas (HPCA, 2011)

A Comprehensive Tapered buffer optimization algorithm for unified design metrics. - Song Liu; Seda Ogrenci Memik; Yehea I. Ismail (ISCAS, 2011)

A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis. - Alberto A. Del Barrio; Seda Ogrenci Memik; María C. Molina; Jose Manuel Mendias; Román Hermida (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Multispeculative Addition Applied to Datapath Synthesis. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik; José M. Mendías; María C. Molina (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Multispeculative additive trees in high-level synthesis. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik; Jose Manuel Mendias; María C. Molina (DATE, 2013)

Exploring the energy efficiency of Multispeculative Adders. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik (ICCD, 2013)

Integrating thermocouple sensors into 3D ICs. - Dawei Li; Ji-Hoon Kim; Seda Ogrenci Memik (ICCD, 2013)

Exploring super-resolution implementations across multiple platforms. - Brian Leung; Seda Ogrenci Memik (EURASIP J. Adv. Signal Process., 2013)

A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths. - Alberto A. Del Barrio; Seda Ogrenci Memik; María C. Molina; José M. Mendías; Román Hermida (Integr., 2013)

Theory and Analysis for Optimization of On-Chip Thermoelectric Cooling Systems. - Jieyi Long; Dawei Li; Seda Ogrenci Memik; Semail Ülgen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Improving circuit performance with multispeculative additive trees in high-level synthesis. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik; Jose Manuel Mendias; María C. Molina (Microelectron. J., 2014)

Edge importance identification for energy efficient graph processing. - S. M. Faisal; Georgios Tziantzioulis; Ali Murat Gok; Nikolaos Hardavellas; Seda Ogrenci Memik; Srinivasan Parthasarathy 001 (IEEE BigData, 2015)

b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units. - Georgios Tziantzioulis; Ali Murat Gok; S. M. Faisal; Nikolaos Hardavellas; Seda Ogrenci Memik; Srinivasan Parthasarathy 001 (DAC, 2015)

User-specific skin temperature-aware DVFS for smartphones. - Begum Egilmez; Gokhan Memik; Seda Ogrenci Memik; Oguz Ergin (DATE, 2015)

A methodology for power characterization of associative memories. - Dawei Li; Siddhartha Joshi; Seda Ogrenci Memik; James Hoff; Sergo Jindariani; Tiehui Liu 001; Jamieson Olsen; Nhan Tran (ICCD, 2015)

Minimizing Thermal Variation Across System Components. - Kaicheng Zhang; Seda Ogrenci Memik; Gokhan Memik; Kazutomo Yoshii; Rajesh Sankaran; Peter H. Beckman (IPDPS, 2015)

On-chip integration of thermoelectric energy harvesting in 3D ICs. - Dawei Li; Seda Ogrenci Memik; Lawrence J. Henschen (ISCAS, 2015)

Lazy Pipelines: Enhancing quality in approximate computing. - Georgios Tziantzioulis; Ali Murat Gok; S. M. Faisal; Nikolaos Hardavellas; Seda Ogrenci Memik; Srinivasan Parthasarathy 001 (DATE, 2016)

A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik (IEEE Trans. Computers, 2016)

Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches. - Dawei Li; Kaicheng Zhang; Akhil Guliani; Seda Ogrenci Memik (DAC, 2017)

Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench. - Yingyi Luo; Xianshan Wen; Kazutomo Yoshii; Seda Ogrenci Memik; Gokhan Memik; Hal Finkel; Franck Cappello (FPL, 2017)

Cell-to-array thermal-aware analysis of stacked RRAM. - Yingyi Luo; Seda Ogrenci Memik; Jie Gu (ISCAS, 2017)

A content addressable memory with multi-Vdd scheme for low power tunable operation. - Siddhartha Joshi; Dawei Li; Seda Ogrenci Memik; Grzegorz Deptuch; James Hoff; Sergo Jindariani; Tiehui Liu 001; Jamieson Olsen; Nhan Tran (MWSCAS, 2017)

End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs. - Dawei Li; Siddhartha Joshi; Ji-Hoon Kim; Seda Ogrenci Memik (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Minimizing Thermal Variation in Heterogeneous HPC Systems with FPGA Nodes. - Yingyi Luo; Xiaoyang Wang; Seda Ogrenci Memik; Gokhan Memik; Kazutomo Yoshii; Peter H. Beckman (ICCD, 2018)

Machine Learning-Based Temperature Prediction for Runtime Thermal Management Across System Components. - Kaicheng Zhang; Akhil Guliani; Seda Ogrenci Memik; Gokhan Memik; Kazutomo Yoshii; Rajesh Sankaran; Peter H. Beckman (IEEE Trans. Parallel Distributed Syst., 2018)

A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree. - Farah Fahim; Siddhartha Joshi; Seda Ogrenci-Memik; Hooman Mohseni (IEEE Trans. Very Large Scale Integr. Syst., 2020)

hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices. - Farah Fahim; Benjamin Hawks; Christian Herwig; James Hirschauer; Sergo Jindariani; Nhan Tran; Luca P. Carloni; Giuseppe Di Guglielmo; Philip C. Harris; Jeffrey D. Krupa; Dylan S. Rankin; Manuel Blanco Valentin; et al. (CoRR, 2021)

A reconfigurable neural network ASIC for detector front-end data compression at the HL-LHC. - Giuseppe Di Guglielmo; Farah Fahim; Christian Herwig; Manuel Blanco Valentin; Javier M. Duarte; Cristian Gingu; Philip C. Harris; James Hirschauer; Martin Kwok; Vladimir Loncar; Yingyi Luo; Llovizna Miranda; et al. (CoRR, 2021)

Applications and Techniques for Fast Machine Learning in Science. - Allison McCarn Deiana; Nhan Tran; Joshua Agar; Michaela Blott; Giuseppe Di Guglielmo; Javier M. Duarte; Philip C. Harris; Scott Hauck; Mia Liu; Mark S. Neubauer; Jennifer Ngadiuba; Seda Ogrenci Memik; et al. (CoRR, 2021)

Thermal Management for FPGA Nodes in HPC Systems. - Yingyi Luo; Joshua C. Zhao; Arnav Aggarwal; Seda Ogrenci-Memik; Kazutomo Yoshii (ACM Trans. Design Autom. Electr. Syst., 2021)

Applications and Techniques for Fast Machine Learning in Science. - Allison McCarn Deiana; Nhan Tran; Joshua Agar; Michaela Blott; Giuseppe Di Guglielmo; Javier M. Duarte; Philip C. Harris; Scott Hauck; Mia Liu; Mark S. Neubauer; Jennifer Ngadiuba; Seda Ogrenci Memik; et al. (Frontiers Big Data, 2022)

A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors. - Adam Quinn; Manuel Blanco Valentin; Thomas Zimmerman 002; Davide Braga; Seda Ogrenci Memik; Farah Fahim (ISCAS, 2023)

Beyond PID Controllers: PPO with Neuralized PID Policy for Proton Beam Intensity Control in Mu2e. - Chenwei Xu; Jerry Yao-Chieh Hu; Aakaash Narayanan; Mattson Thieme; Vladimir Nagaslaev; Mark Austin; Jeremy Arnold; Jose Berlioz; Pierrick Hanlet; Aisha Ibrahim; Dennis Nicklaus; Jovan Mitrevski; et al. (CoRR, 2023)

ML-Based Real-Time Control at the Edge: An Approach Using hls4ml. - Rui Shi; Seda Ogrenci; J. M. Arnold; J. R. Berlioz; Pierrick Hanlet; Kyle J. Hazelwood; M. A. Ibrahim; Han Liu 001; V. P. Nagaslaev; Aakaash Narayanan; D. J. Nicklaus; Jovan Mitrevski; et al. (IPDPS (Workshops), 2024)

A High Level Synthesis Methodology for Dynamic Monitoring of FPGA ML Accelerators. - Ryan F. Forelli; Rui Shi; Seda Ogrenci; Joshua Agar (VTS, 2024)

Corrigendum: Applications and techniques for fast machine learning in science. - Allison McCarn Deiana; Nhan Tran; Joshua Agar; Michaela Blott; Giuseppe Di Guglielmo; Javier M. Duarte; Philip C. Harris; Scott Hauck; Mia Liu; Mark S. Neubauer; Jennifer Ngadiuba; Seda Ogrenci-Memik; et al. (Frontiers Big Data, 2024)

Toward Reconfigurable In-Pixel Computing: A Fault-Tolerant Design Flow for Machine Learning Accelerators: (Invited Paper). - Houxuan Guo; Manuel Blanco Valentin; Xiuyuan He; Seda Ogrenci (FCCM, 2025)

SPRING: Systematic Profiling of Randomly Interconnected Neural Networks Generated by HLS. - Rui Shi; Seda Ogrenci (VTS, 2025)

Real-Time Cell Sorting with Scalable In Situ FPGA-Accelerated Deep Learning. - Khayrul Islam; Ryan F. Forelli; Jianzhong Han; Deven Bhadane; Jian Huang; Joshua C. Agar; Nhan Tran; Seda Ogrenci; Yaling Liu (CoRR, 2025)