Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. - Seetal Potluri; Nitin Chandrachoodan; V. Kamakoti 001 (ISVLSI, 2011)

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. - Rama Kumar Pasumarthi; V. R. Devanathan; V. Visvanathan; Seetal Potluri; V. Kamakoti 001 (J. Low Power Electron., 2012)

Interconnect Aware Test Power Reduction. - Seetal Potluri; Nitin Chandrachoodan; V. Kamakoti 001 (J. Low Power Electron., 2012)

PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information. - Seetal Potluri; Satya Trinadh; Roopashree Baskaran; Nitin Chandrachoodan; V. Kamakoti 001 (ETS, 2013)

LPScan: An algorithm for supply scaling and switching activity minimization during test. - Seetal Potluri; Satya Trinadh Adireddy; Chidhambaranathan Rajamanikkam; Shankar Balachandran (ICCD, 2013)

An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test. - Satya Trinadh; Seetal Potluri; Ch. Sobhan Babu; V. Kamakoti 001 (J. Low Power Electron., 2013)

XStat: Statistical X-Filling Algorithm for Peak Capture Power Reduction in Scan Tests. - Satya Trinadh; Seetal Potluri; Shankar Balachandran; Ch. Sobhan Babu; V. Kamakoti 001 (J. Low Power Electron., 2014)

DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests. - Satya Trinadh; Ch. Sobhan Babu; Shiv Govind Singh; Seetal Potluri; V. Kamakoti 001 (DATE, 2015)

DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing. - Seetal Potluri; Satya Trinadh; Ch. Sobhan Babu; V. Kamakoti 001; Nitin Chandrachoodan (ACM Trans. Design Autom. Electr. Syst., 2015)

Architecture synthesis for cost-constrained fault-tolerant flow-based biochips. - Morten Chabert Eskesen; Paul Pop; Seetal Potluri (DATE, 2016)

Component fault localization using switching current measurements. - Seetal Potluri; Satya Trinadh; Siddhant Saraf; Kamakoti Veezhinathan (ETS, 2016)

Power Consumption versus Hardware Security: Feasibility Study of Differential Power Attack on Linear Feedback Shift Register Based Stream Ciphers and Its Countermeasures. - Sanjay Burman; Seetal Potluri; Debdeep Mukhopadhyay; Kamakoti Veezhinathan (J. Low Power Electron., 2016)

Cell-Aware ATPG to Improve Defect Coverage for FPGA IPs and Next Generation Zynq® MPSoCs. - Seetal Potluri; Aaron Mathew; Rambabu Nerukonda; Ismed Hartanto; Shahin Toutounchi (ATS, 2017)

Synthesis of on-chip control circuits for mVLSI biochips. - Seetal Potluri; Alexander Schneider 002; Martin Horslev-Petersen; Paul Pop; Jan Madsen (DATE, 2017)

A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips. - Gokulkrishnan Vadakkeveedu; V. Kamakoti 001; Nitin Chandrachoodan; Seetal Potluri (DFT, 2017)

BioChipWork: Reverse Engineering of Microfluidic Biochips. - Huili Chen; Seetal Potluri; Farinaz Koushanfar (ICCD, 2017)

Optimal Don't Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing. - Satya Trinadh Adireddy; Seetal Potluri; Ch. Sobhan Babu; Veezhinathan Kamakoti; Shiv Govind Singh (ACM Trans. Design Autom. Electr. Syst., 2017)

MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis. - Patanjali SLPSK; Milan Patnaik; Seetal Potluri; V. Kamakoti 001 (J. Low Power Electron., 2018)

Design-for-Testability of On-Chip Control in mVLSI Biochips. - Seetal Potluri; Paul Pop; Jan Madsen (IEEE Des. Test, 2019)

Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-. - Francesco Regazzoni 001; Shivam Bhasin; Amir Alipour; Ihab Alshaer; Furkan Aydin; Aydin Aysu; Vincent Beroulle; Giorgio Di Natale; Paul D. Franzon; David Hély; Naofumi Homma; Akira Ito 002; et al. (ICCAD, 2020)

Efficacy of Satisfiability-Based Attacks in the Presence of Circuit Reverse-Engineering Errors. - Qinhan Tan; Seetal Potluri; Aydin Aysu (ISCAS, 2020)

SeqL: Secure Scan-Locking for IP Protection. - Seetal Potluri; Aydin Aysu; Akash Kumar 001 (ISQED, 2020)

FlowTrojan: Insertion and Detection of Hardware Trojans on Flow-Based Microfluidic Biochips. - Huili Chen; Seetal Potluri; Farinaz Koushanfar (NEWCAS, 2020)

DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks. - Furkan Aydin; Priyank Kashyap; Seetal Potluri; Paul D. Franzon; Aydin Aysu (SAMOS, 2020)

Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips. - Gokulkrishnan Vadakkeveedu; Kamakoti Veezhinathan; Nitin Chandrachoodan; Seetal Potluri (IET Comput. Digit. Tech., 2020)

Security of Microfluidic Biochip: Practical Attacks and Countermeasures. - Huili Chen; Seetal Potluri; Farinaz Koushanfar (ACM Trans. Design Autom. Electr. Syst., 2020)

iTimed: Cache Attacks on the Apple A10 Fusion SoC. - Gregor Haas; Seetal Potluri; Aydin Aysu (IACR Cryptol. ePrint Arch., 2021)

Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware. - Seetal Potluri; Aydin Aysu (IACR Cryptol. ePrint Arch., 2021)

2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning. - Priyank Kashyap; Furkan Aydin; Seetal Potluri; Paul D. Franzon; Aydin Aysu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

PR Crisis: Analyzing and Fixing Partial Reconfiguration in Multi-Tenant Cloud FPGAs. - Emre Karabulut; Chandu Yuvarajappa; Mohammed Iliyas Shaik; Seetal Potluri; Amro Awad; Aydin Aysu (ASHES@CCS, 2022)

Towards AI-Enabled Hardware Security: Challenges and Opportunities. - Hossein Sayadi; Mehrdad Aliasgari; Furkan Aydin; Seetal Potluri; Aydin Aysu; Jack Edmonds 002; Sara Tehranipoor (IOLTS, 2022)

RevEAL: Single-Trace Side-Channel Leakage of the SEAL Homomorphic Encryption Library. - Furkan Aydin; Emre Karabulut; Seetal Potluri; Erdem Alkim; Aydin Aysu (IACR Cryptol. ePrint Arch., 2022)

Scalable Scan-Chain-Based Extraction of Neural Network Models. - Shui Jiang; Seetal Potluri; Tsung-Yi Ho (DATE, 2023)

SeqL+: Secure Scan-Obfuscation With Theoretical and Empirical Validation. - Seetal Potluri; Shamik Kundu; Akash Kumar 001; Kanad Basu; Aydin Aysu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

SoK: Model Reverse Engineering Threats for Neural Network Hardware. - Seetal Potluri; Farinaz Koushanfar (IACR Cryptol. ePrint Arch., 2024)