EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression. - Seetharaman Ramachandran; S. Srinivasan 001; R. Chen (ISCAS (3), 1999)

Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. - D. V. R. Murthy; Seetharaman Ramachandran; S. Srinivasan 001 (VLSI Design, 1999)

A programmable pruning level control based MPEG video encoder. - Seetharaman Ramachandran; S. Srinivasan 001 (ISCAS, 2000)

Design and implementation of an EPLD-based variable length coder for real time image compression applications. - Seetharaman Ramachandran; S. Srinivasan 001 (ISCAS, 2000)

FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. - Seetharaman Ramachandran; S. Srinivasan 001 (FPGA, 2001)

A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme. - Seetharaman Ramachandran; S. Srinivasan 001 (Microprocess. Microsystems, 2002)

A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism. - Seetharaman Ramachandran; S. Srinivasan 001 (VLSI Design, 2002)

A Novel, Automatic Quality Control Scheme for Real Time Image Transmission. - Seetharaman Ramachandran; S. Srinivasan 001 (VLSI Design, 2002)

Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization. - Seetharaman Ramachandran; S. Srinivasan 001 (DSD, 2003)

Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. - Seetharaman Ramachandran; S. Srinivasan 001 (J. Syst. Archit., 2005)

Tsallis entropy and particle swarm optimization-based cyclone image vortex localization. - Harish Anil Jamakhandi; Tilak D.; Manikantan K.; Seetharaman Ramachandran (ICACCI, 2015)