Results on the Interface between Formal Verification and ATPG. - Hyunwoo Cho; Gary D. Hachtel; Seh-Woong Jeong; Bernard Plessier; Eric M. Schwarz; Fabio Somenzi (CAV (DIMACS/AMS volume), 1990)

ATPG Aspects of FSM Verification. - Hyunwoo Cho; Gary D. Hachtel; Seh-Woong Jeong; Bernard Plessier; Eric M. Schwarz; Fabio Somenzi (ICCAD, 1990)

Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms. - Seh-Woong Jeong; Bernard Plessier; Gary D. Hachtel; Fabio Somenzi (ICCAD, 1991)

Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. - Carl Pixley; Seh-Woong Jeong; Gary D. Hachtel (DAC, 1992)

A new algorithm for the binate covering problem and its application to the minimization of Boolean relations. - Seh-Woong Jeong; Fabio Somenzi (ICCAD, 1992)

Synchronizing sequences and symbolic traversal techniques in test generation. - Hyunwoo Cho; Seh-Woong Jeong; Fabio Somenzi; Carl Pixley (J. Electron. Test., 1993)

Exact calculation of synchronizing sequences based on binary decision diagrams. - Carl Pixley; Seh-Woong Jeong; Gary D. Hachtel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

CalmRISCTM: A Low Power Microcontroller with Efficient Coprocessor Interface. - Kyoung-Mook Lim; Seh-Woong Jeong; Yong-Chun Kim; Seung-Jae Jeong; Hong-Kyu Kim; Yang-Ho Kim; Bong-Young Chung; Hyung-Lae Roh; H. S. Yang (ICCD, 1999)

A Low-Power Cache Design for CalmRISCTM-Based Systems. - Sangyeun Cho; Wooyoung Jung; Yongchun Kim; Seh-Woong Jeong (ICCD, 2001)

A Banked-Promotion TLB for High Performance and Low Power. - Jung-Hoon Lee; Jang-Soo Lee; Seh-Woong Jeong; Shin-Dug Kim (ICCD, 2001)

Reducing Cache Pollution of Prefetching in a Small Data Cache. - Pipat Reungsang; Sun Kyu Park; Seh-Woong Jeong; Hyung-Lae Roh; Gyungho Lee (ICCD, 2001)

CalmRISCTM: a low power microcontroller with efficient coprocessor interface. - Kyoung-Mook Lim; Seh-Woong Jeong; Yong-Chun Kim; H. S. Yang (Microprocess. Microsystems, 2001)

Grouped zerotree wavelet image coding for very low bit rate. - Woo-Young Jang; Byung-Hoan Chon; Seh-Woong Jeong; Kwanghoon Sohn (ICIP (3), 2002)

A Low Power TLB Structure for Embedded Systems. - Jin-Hyuck Choi; Jung-Hoon Lee; Seh-Woong Jeong; Shin-Dug Kim; Charles C. Weems (IEEE Comput. Archit. Lett., 2002)

A banked-promotion translation lookaside buffer system. - Jung-Hoon Lee; Seh-Woong Jeong; Shin-Dug Kim; Charles C. Weems (J. Syst. Archit., 2002)

An Intelligent Cache System with Hardware Prefetching for High Performance. - Jung-Hoon Lee; Seh-Woong Jeong; Shin-Dug Kim; Charles C. Weems (IEEE Trans. Computers, 2003)

An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications. - Donghyun Kim 014; Kyusik Chung; Chang-Hyo Yu; Chun-Ho Kim; Inho Lee; Jaewan Bae; Young-Jun Kim 001; Jae-Hyeon Park; Sungbeen Kim; Yong-Ha Park; Nak Hee Seong; Jin-Aeon Lee; et al. (IEEE J. Solid State Circuits, 2006)

A 40-to-800MHz Locking Multi-Phase DLL. - Young-Sang Kim; Seung-Jin Park; Yong-Sub Kim; Dong-Bi Jang; Seh-Woong Jeong; Hong-June Park; Jae-Yoon Sim (ISSCC, 2007)

In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem. - Woo-Cheol Kwon; Sungjoo Yoo; Junhyung Um; Seh-Woong Jeong (DATE, 2009)