10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm. - Seheon Jang; Munjae Chae; Hangi Park; Chanwoong Hwang; Jaehyouk Choi (ISSCC, 2024)

A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm. - Seheon Jang; Munjae Chae; Hangi Park; Chanwoong Hwang; Jaehyouk Choi (IEEE J. Solid State Circuits, 2024)

34.1 A 65fsrms-Jitter and -272dB-FoMjitter, N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration. - Munjae Chae; Seheon Jang; Chanwoong Hwang; Hangi Park; Jaehyouk Choi (ISSCC, 2025)