Memory-Efficient Compressed Filesystem Architecture for NAND Flash-Based Embedded Systems. - Seunghwan Hyun; Sungyong Ahn; Sehwan Lee; Hyokyung Bahn; Kern Koh (ICCSA (1), 2007)

Improving the Demand Paging Performance with NAND-type Flash Memory. - Seunghwan Hyun; Sehwan Lee; Sungyong Ahn; Kern Koh (ICCSA Workshops, 2008)

Vector Read: Exploiting the Read Performance of Hybrid NAND Flash. - Seunghwan Hyun; Sehwan Lee; Sungyong Ahn; Hyokyung Bahn; Kern Koh (RTCSA, 2008)

Selective Context Switching on Flash Memory. - Sehwan Lee; Seunghwan Hyun; Kern Koh (ICCSA Workshops, 2009)

Unifying Buffer Replacement and Prefetching with Data Migration for Heterogeneous Storage Devices. - Sehwan Lee; Kern Koh; Hyokyung Bahn (ICPADS, 2010)

A Demand-Based FTL Scheme Using Dualistic Approach on Data Blocks and Translation Blocks. - Sehwan Lee; Bitna Lee; Kern Koh; Hyokyung Bahn (RTCSA (1), 2011)

A lifespan-aware reliability scheme for RAID-based flash storage. - Sehwan Lee; Bitna Lee; Kern Koh; Hyokyung Bahn (SAC, 2011)

Does Spatial Attribute between 2D and 3D Virtual Spaces make Different User Immersion of Audio-Visual Events? - Sehwan Lee; Ju-Hwan Lee (ICCAE, 2017)

A Wearable Electrocardiogram Monitoring System Robust to Motion Artifacts. - Taeryoung Seol; Sehwan Lee; Junghyup Lee (ISOCC, 2018)

A 110dB-CMRR 100dB-PSRR multi-channel neural-recording amplifier system using differentially regulated rejection ratio enhancement in 0.18μm CMOS. - Sehwan Lee; Arup K. George; Taeju Lee; Jun-Uk Chu; Sungmin Han; Ji-Hoon Kim 003; Minkyu Je; Junghyup Lee (ISSCC, 2018)

An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sparsity-Aware Neural Processing Unit in 8nm Flagship Mobile SoC. - Jinook Song; Yunkyo Cho; Jun-Seok Park; Jun-Woo Jang; Sehwan Lee; Joon-Ho Song; Jae-Gon Lee; Inyup Kang (ISSCC, 2019)

A Systolic Dataflow Based Accelerator for CNNs. - Saptarsi Das; Arnab Roy 010; Kiran Kolar Chandrasekharan; Ankur Deshwal; Sehwan Lee (ISCAS, 2020)

Accelerating Depthwise Convolution and Pooling Operations on z-First Storage CNN Architectures. - Pramod P. Udupa; Gopinath Mahale; Kiran Kolar Chandrasekharan; Sehwan Lee (ISCAS, 2020)

A Multi-Mode ULP Receiver Based on an Injection-Locked Oscillator for IoT Applications. - Soonyoung Hong; Sehwan Lee; Junghyup Lee; Minkyu Je (IEEE Access, 2020)

IKW: Inter-Kernel Weights for Power Efficient Edge Computing. - Pramod P. Udupa; Gopinath Mahale; Kiran Kolar Chandrasekharan; Sehwan Lee (IEEE Access, 2020)

WinDConv: A Fused Datapath CNN Accelerator for Power-Efficient Edge Devices. - Gopinath Mahale; Pramod P. Udupa; Kiran Kolar Chandrasekharan; Sehwan Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Sparsity-Aware and Re-configurable NPU Architecture for Samsung Flagship Mobile SoC. - Jun-Woo Jang; Sehwan Lee; Dongyoung Kim; Hyunsun Park; Ali Shafiee Ardestani; Yeongjae Choi; Channoh Kim; Yoojin Kim; Hyeongseok Yu; Hamzah Abdel-Aziz; Jun-Seok Park; Heonsoo Lee; et al. (ISCA, 2021)

9.5 A 6K-MAC Feature-Map-Sparsity-Aware Neural Processing Unit in 5nm Flagship Mobile SoC. - Jun-Seok Park; Jun-Woo Jang; Heonsoo Lee; Dongwoo Lee; Sehwan Lee; Hanwoong Jung; Seungwon Lee; Suknam Kwon; Kyung-Ah Jeong; Joon-Ho Song; Sukhwan Lim; Inyup Kang (ISSCC, 2021)

A 0.7V 17fJ/Step-FOMW 178.1dB-FOMSNDR 10kHz-BW 560mVPP True-ExG Biopotential Acquisition System with Parasitic-Insensitive 421MΩ Input Impedance in 0.18μm CMOS. - Sehwan Lee; Yoonsung Choi; Geunha Kim; Seungyeob Baik; Taeryoung Seol; Homin Jang; Doyoung Lee; Minkyu Je; Ji-Woong Choi; Arup K. George; Junghyup Lee (ISSCC, 2022)

A 2.54μJ∙ppm2-FOMS Supply- and Temperature-Independent Time-Locked ΔΣ Capacitance-to-Digital Converter in 0.18-μm CMOS. - Seungyeob Baik; Taeryoung Seol; Sehwan Lee; Geunha Kim; SeongHwan Cho; Arup K. George; Junghyup Lee (VLSI Technology and Circuits, 2022)

A 1V-Supply $1.85 mathrm{V}_{ text{PP}}$ -Input-Range 1kHz-BW 181.9dB-FOMDR179.4dB-FOMSNDR 2nd-Order Noise-Shaping SAR-ADC with Enhanced Input Impedance in 0.18μm CMOS. - Geunha Kim; Sehwan Lee; Taeryoung Seol; Seungyeob Baik; Yeonjae Shin; Gain Kim; Jong-Hyeok Yoon; Arup K. George; Junghyup Lee (ISSCC, 2023)

A 1V 136.6dB-DR 4kHz-BW $ Delta Sigma$ Current-to-Digital Converter with a Truncation-Noise-Shaped Baseline-Servo-Loop in 0.18 mu mathrm{m}$ CMOS. - Taeryoung Seol; Sehwan Lee; Geunha Kim; Samhwan Kim; Euiseong Kim; Seungyeob Baik; Jaeha Kung; Ji-Woong Choi; Arup K. George; Junghyup Lee (ISSCC, 2023)

A 3.3-to-11V-Supply-Range 10μW/Ch Arbitrary-Waveform-Capable Neural Stimulator with Output-Adaptive-Self-Bias and Supply-Tracking Schemes in 0.18μm Standard CMOS. - Jeongyoon Wie; Sangwoo Jung; Taeryoung Seol; Geunha Kim; Sehwan Lee; Homin Jang; Samhwan Kim; Yeonjae Shin; Jae Eun Jang; Jaeha Kung; Arup K. George; Junghyup Lee (CICC, 2024)

33.11 A Hybrid Recording System with 10kHz-BW 630mVPP 84.6dB-SNDR 173.3dB-FOMSNDR and 5kHz-BW 114dB-DR for Simultaneous ExG and Biocurrent Acquisition. - Taeryoung Seol; Geunha Kim; Sehwan Lee; Samhwan Kim; Dongwook Kim; Jeongyoon Wie; Yeonjae Shin; Hongki Kang; Jae Eun Jang; Arup K. George; Junghyup Lee (ISSCC, 2024)

A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCO-ΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition. - Sehwan Lee; Taeryoung Seol; Geunha Kim; Minyoung Song; Gain Kim; Jong-Hyeok Yoon; Arup K. George; Junghyup Lee (VLSI Technology and Circuits, 2024)