Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops. - Jaejoon Yoon; Sehyeon Chung; Taewhan Kim 001 (ISOCC, 2021)

Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. - Sehyeon Chung; Jooyeon Jeong; Taewhan Kim 001 (ISLPED, 2022)

Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. - Suwan Kim; Sehyeon Chung; Taewhan Kim 001; Heechun Park (ISLPED, 2022)

ECO routing based on network flow method. - Sehyeon Chung; Taewhan Kim 001 (Integr., 2022)

Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. - Jooyeon Jeong; Sehyeon Chung; Kyeongrok Jo; Taewhan Kim 001 (DATE, 2023)

Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. - Handong Cho; Hyunbae Seo; Sehyeon Chung; Kyu-Myung Choi; Taewhan Kim 001 (DATE, 2024)

Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes. - Sehyeon Chung; Hyunbae Seo; Handong Cho; Kyumyung Choi; Taewhan Kim 001 (ICCAD, 2024)