Negative Gate Bias TDDB evaluation of n-Channel SiC Vertical Power MOSFETs. - Satyaki Ganguly; Daniel J. Lichtenwalner; Caleb Isaacson; Donald A. Gajewski; Philipp Steinmann; Ryan Foarde; Brett Hull; Sei-Hyung Ryu; Scott Allen; John W. Palmour (IRPS, 2022)

Modeling of the Snappy, and Soft Reverse Recovery of SiC MOSFET's Body Diode. - Arman Ur Rashid; Britt Brooks; Steven Manz; Daniel J. Lichtenwalner; Sei-Hyung Ryu (BCICTS, 2023)

Characterization of Interface Trap Density in SiC MOSFETs Subjected to High Voltage Gate Stress. - S. R. Stein; J. Kim; Suman Das; Daniel J. Lichtenwalner; Sei-Hyung Ryu (IRPS, 2024)

Measurement of the $D_{it}$ Changes Under BTI-Stress in 4H-SiC FETs Using the Subthreshold Slope Method. - Philipp Steinmann; Daniel J. Lichtenwalner; Shane Stein; Jae-Hyung Park; Suman Das; Sei-Hyung Ryu (IRPS, 2024)