A methodology for statistical estimation of read access yield in SRAMs. - Mohamed H. Abu-Rahma; Kinshuk Chowdhury; Joseph Wang; Zhiqin Chen; Sei Seung Yoon; Mohab Anis (DAC, 2008)

A robust single supply voltage SRAM read assist technique using selective precharge. - Mohamed H. Abu-Rahma; Mohab Anis; Sei Seung Yoon (ESSCIRC, 2008)

Reducing SRAM Power Using Fine-Grained Wordline Pulsewidth Control. - Mohamed H. Abu-Rahma; Mohab Anis; Sei Seung Yoon (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS. - Mohamed H. Abu-Rahma; Ying Chen; Wing Sy; Wee Ling Ong; Leon Yeow Ting; Sei Seung Yoon; Michael Han 002; Esin Terzioglu (CICC, 2011)

Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technology. - Animesh Datta; Mohamed H. Abu-Rahma; Sachin Dileep Dasnurkar; Hadi Rasouli; Sean Tamjidi; Ming Cai; Samit Sengupta; P. R. Chidambaram; Raghavan Thirumala; Nikhil Kulkarni; Prasanna Seeram; Prasad Bhadri; et al. (ISQED, 2013)

Experiments and analysis to characterize logic state retention limitations in 28nm process node. - Sachin Dileep Dasnurkar; Animesh Datta; Mohamed H. Abu-Rahma; Hieu Nguyen; Martin Villafana; Hadi Rasouli; Sean Tamjidi; Ming Cai; Samit Sengupta; P. R. Chidambaram; Raghavan Thirumala; Nikhil Kulkarni; et al. (VTS, 2013)

Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors. - Alex Park 002; Venkat Narayanan; Keith A. Bowman; Francois Atallah; Alain Artieri; Sei Seung Yoon; Kendrick Yuen; David Hansquine (CICC, 2014)

Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors. - Keith A. Bowman; Alex Park 002; Venkat Narayanan; Francois Atallah; Alain Artieri; Sei Seung Yoon; Kendrick Yuen; David Hansquine (ITC, 2014)

A 14nm 128Mb Embedded MRAM Macro achieved the Best Figure-Of-Merit with 80MHz Read operation and 18.1Mb/mm² implementation at 0.64V. - Gyuseong Kang; Hyunjin Shin; Hyuntaek Jung; Sunkyu Lee; Jaeseung Choi 001; Sangyeop Baeck; Hyunsung Jung; Daeshik Kim; Sohee Hwang; Shinhee Han; Yongsung Ji; Sei Seung Yoon (VLSI Technology and Circuits, 2023)

A 14nm 128Mb eMRAM Implemented with 17.88Mb/mm2 at 0.60V for Auto-G1 Applications. - Gyuseong Kang; Hyunjin Shin; Sanggyeong Won; Dohui Kim; Kyuseong Kim; Soohoh Seol; Sunkyu Lee; Hangil Lee; Yeonho Jung; Jaechul Shim; Kiseok Suh; Sohee Hwang; et al. (VLSI Technology and Circuits, 2024)