Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. - Seian-Feng Liao; Kai-Neng Tang; Ming-Dou Ker; Jia-Rong Yeh; Hwa-Chyi Chiou; Yeh-Jen Huang; Chun-Chien Tsai; Yeh-Ning Jou; Geeng-Lih Lin (ECCTD, 2015)