Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. - Yoshiki Saito; Tomoaki Shirai; Takuro Nakamura; Takashi Nishimura; Yohei Hasegawa; Satoshi Tsutsumi; Toshihiro Kashima; Mitsutaka Nakata; Seidai Takeda; Kimiyoshi Usami; Hideharu Amano (FPT, 2008)

A fine-grain dynamic sleep control scheme in MIPS R3000. - Naomi Seki; Lei Zhao; Jo Kei; Daisuke Ikebuchi; Yu Kojima; Yohei Hasegawa; Hideharu Amano; Toshihiro Kashima; Seidai Takeda; Toshiaki Shirai; Mitsutaka Nakata; Kimiyoshi Usami; et al. (ICCD, 2008)

Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. - Kimiyoshi Usami; Toshiaki Shirai; Tatsunori Hashida; Hiroki Masuda; Seidai Takeda; Mitsutaka Nakata; Naomi Seki; Hideharu Amano; Mitaro Namiki; Masashi Imai; Masaaki Kondo; Hiroshi Nakamura (VLSI Design, 2009)

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. - Daisuke Ikebuchi; Naomi Seki; Yu Kojima; M. Kamata; Lei Zhao; Hideharu Amano; Toshiaki Shirai; Satoshi Koyama; Tatsunori Hashida; Y. Umahashi; Hiroki Masuda; Kimiyoshi Usami; et al. (ASP-DAC, 2010)

Geyser-2: The second prototype CPU with fine-grained run-time power gating. - Lei Zhao; Daisuke Ikebuchi; Yoshiki Saito; M. Kamata; Naomi Seki; Yu Kojima; Hideharu Amano; Satoshi Koyama; Tatsunori Hashida; Y. Umahashi; D. Masuda; Kimiyoshi Usami; et al. (ASP-DAC, 2011)

Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model. - Seidai Takeda; Kyundong Kim; Hiroshi Nakamura; Kimiyoshi Usami (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A novel power-gating scheme utilizing data retentiveness on caches. - Kyundong Kim; Seidai Takeda; Shinobu Miwa; Hiroshi Nakamura (ACM Great Lakes Symposium on VLSI, 2012)

Stepwise sleep depth control for run-time leakage power saving. - Seidai Takeda; Shinobu Miwa; Kimiyoshi Usami; Hiroshi Nakamura (ACM Great Lakes Symposium on VLSI, 2012)

Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. - Seidai Takeda; Shinobu Miwa; Kimiyoshi Usami; Hiroshi Nakamura (ISQED, 2012)

Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches. - Kyundong Kim; Seidai Takeda; Shinobu Miwa; Hiroshi Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)