30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit. - Gensoh Matsubara; Nobuhiro Ide; Haruyuki Tago; Seigo Suzuki; Nobuyuki Goto (IEEE Symposium on Computer Arithmetic, 1995)

A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor. - Masafumi Takahashi; Hiroyuki Takano; Emi Kaneko; Seigo Suzuki (HPCA, 1996)