A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design. - Kenichi Imamiya; Jun-ichi Miyamoto; Shigeru Atsumi; Nobuaki Ohtsuka; Yukinori Muroya; Toshiyuki Sako; Masao Higashino; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Hitoshi Araki; Yukio Kaneko; et al. (IEEE J. Solid State Circuits, 1990)

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique. - Naoto Tomita; Nobuaki Ohtsuka; Jun-ichi Miyamoto; Ken-ichi Imamiya; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Norihisa Arai; Yukio Kaneko; Eiji Sakagami; Kuniyoshi Yoshikawa; Sumio Tanaka (IEEE J. Solid State Circuits, 1991)

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. - Shigeru Atsumi; Akira Umezawa; Toru Tanzawa; Tadayuki Taura; Hitoshi Shiga; Yoshinori Takano; Takeshi Miyaba; Michiharu Matsui; Hiroshi Watanabe; Kazuaki Isobe; Shota Kitamura; Seiji Yamada; et al. (IEEE J. Solid State Circuits, 2000)

Irregularities in Candidates Selection of Multi-Aimed University Entrance Examinations. - Takahiko Suzuki; Takeshi Michiwaki; Keiji Ayukawa; Michiyo Ishimaru; Seiichi Mori (IIAI-AAI, 2013)