A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. - Seiji Miura; Kazushige Ayukawa; Takao Watanabe (ISLPED, 2001)

Elastic shared resource scheduling SOC interconnect architecture for real-time system. - Makoto Saen; Hiroshi Ueda; Masaru Hase; Eiji Yamamoto; Yoshihiro Mori; Hiroshi Hatae; Yuki Kondo; Seiji Miura; Itaru Nonomura; Naohiko Irie; Hiromi Watanabe (CICC, 2005)

A memory controller that reduces latency of cached SDRAM. - Seiji Miura; Satoru Akiyama (ISCAS (5), 2005)

A control scheme for eliminating garbage collection during highspeed analysis of big-graph data stored in NAND flash memory. - Hiroshi Uchigaito; Seiji Miura; Takumi Nito (ISCAS, 2015)

Efficient Data-Allocation Scheme for Eliminating Garbage Collection During Analysis of Big Graphs Stored in NAND Flash Memory. - Hiroshi Uchigaito; Seiji Miura; Takumi Nito (IEEE Trans. Computers, 2018)

Edge devices object detection by filter pruning. - Viviana Crescitelli; Seiji Miura; Goichi Ono; Naohiro Kohmu (ETFA, 2021)