A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates. - Seishi Notomi; Yuu Watanabe; Makoto Kosugi; Isamu Hanyu; Masahisa Suzuki; Takashi Mimura; Masayuki Abe (IEEE J. Solid State Circuits, 1991)

A 1.2-ns HEMT 64-kb SRAM. - Masahisa Suzuki; Seishi Notomi; Masaaki Ono; Naoki Kobayashi; Eizo Mitani; Kouichiro Odani; Takashi Mimura; Masayuki Abe (IEEE J. Solid State Circuits, 1991)