Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. - Kang Wook Lee 002; Seiya Tanikawa; Mariappan Murugesan; H. Naganuma; Jichoel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2013)

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC. - Hisashi Kino; Hideto Hashiguchi; Seiya Tanikawa; Yohei Sugawara; Shunsuke Ikegaya; Takafumi Fukushima; Mitsumasa Koyanagi; Tetsu Tanaka (3DIC, 2015)

Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors. - Seiya Tanikawa; Hisashi Kino; Takafumi Fukushima; Mitsumasa Koyanagi; Tetsu Tanaka (3DIC, 2015)